Microchip LAN9250V/ML
Manufacturer No:
LAN9250V/ML
Manufacturer:
Package:
64-VFQFN Exposed Pad
Description:
The LAN9250 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required.
Quantity:
User Guide
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LAN9250V/ML Information
Microchip LAN9250V/ML technical specifications, attributes, parameters and parts with similar specifications to Microchip LAN9250V/ML.
- Type
- Parameter
- Checksum Offload
- Yes
- DownstreamPorts
- 1
- ESD Rating
- 0
- Port Speed
- 10/100Mbps
- Fiber Support
- Yes
- Interrupt Pin
- 1
- LEDS
- 3
- LinkMDCableDiag
- Yes
- Mixed Endian
- Yes
- NoofEtherPorts
- 0
- Type
- Parameter
- Number of VLANs
- 0
- OpVoltage
- 0
- Supply Voltages
- 0
- TX/RX Ram Buffer
- 16K
- Temperature Range Max
- 105
- Temperature Range Min
- -40
- Digital I/O Voltage
- 1.8/2.5/3.3
Download datasheets and manufacturer documentation for Microchip LAN9250V/ML.
Brochures:
Application Notes:
Data Sheets:
User Guide:
The LAN9250 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9250 has been specifically designed to provide high performance and throughput for 16-bit applications. The LAN9250 complies with the IEEE802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet (EEE) (100Mbps only), and the IEEE 1588v2 precision time protocol. 100BASE-FX is supported via an external fiber transceiver.
The LAN9250 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. For additional design flexibility SPI and SQI interfaces are also supported. The integrated checksum offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames, offloading the task from the CPU. The LAN9250 also includes large transmit and receive data FIFOs to accommodate high latency applications. In addition, the LAN9250 memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity. The LAN9250 also supports features which reduce or eliminate packet loss. The internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9250 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions.
The LAN9250 can be configured to operate via a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system power dissipation
Microchip's complimentary and confidential MicroCHECK design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.
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