INTEL EP1810LC-25T

Manufacturer No:

EP1810LC-25T

Manufacturer:

INTEL

Package:

PLCC

Description:

5.08mm mm FPGAs PLCC 1.27mm mm 68

Quantity:

Delivery:

Payment:

In Stock :Available

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EP1810LC-25T information

INTEL EP1810LC-25T technical specifications, attributes, parameters and parts with similar specifications to INTEL EP1810LC-25T.

Type
Parameter

Package / Case
PLCC

Surface Mount
YES

JESD-609 Code
e0

Pbfree Code
no

Number of Terminations
68

ECCN Code
EAR99

Terminal Finish
Tin/Lead (Sn/Pb)

Additional Feature
MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS

HTS Code
8542.39.00.01

Subcategory
Programmable Logic Devices

Technology
CMOS

Terminal Position
QUAD

Terminal Form
J BEND

Peak Reflow Temperature (Cel)
220

Supply Voltage
5V

Terminal Pitch
1.27mm

Time@Peak Reflow Temperature-Max (s)
30

Pin Count
68

JESD-30 Code
S-PQCC-J68

Qualification Status
Not Qualified

Operating Temperature (Max)
70°C

Supply Voltage-Max (Vsup)
5.25V

Power Supplies
5V

Temperature Grade
COMMERCIAL

Number of I/O
48

Clock Frequency
40MHz

Propagation Delay
28 ns

Organization
12 DEDICATED INPUTS, 48 I/O

Programmable Logic Type
OT PLD

Number of Gates
900

Output Function
MACROCELL

Number of Macro Cells
48

JTAG BST
NO

Number of Dedicated Inputs
12

In-System Programmable
NO

Length
24.23mm

Height Seated (Max)
5.08mm

Width
24.23mm

RoHS Status
RoHS Compliant

Download datasheets and manufacturer documentation for INTEL EP1810LC-25T.

EP1810LC-25T Overview

In the package PLCC, this product is provided. Fpga chips consists of OT PLD elements. A total of 48 I/Os are programmed to ensure a more coherent data transfer. Supply voltage is 5V volts. There is a Programmable Logic Devices family component in this FPGA part. In total, the terminations of this piece are 68. This is a battery operated device that operates on 5V. A basic building block for this type of building block consists of 900 gates. I am going to present you with a device that is equipped with 68 pins. Fpga semiconductor typically uses a crystal oscillating at 40MHz. In addition, it has a feature called MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS. There are a total of 12 dedicated inputs that allow input signals to be detected the status of each input. In order to keep this FPGA operating, its supply voltage should be higher than 4.75V. In this device, the main building blocks of a CPLD are 48 macro cells, which serve as the main components of the device. A maximum operating temperature of 70°C °C should be observed when running the equipment.

EP1810LC-25T Features

48 I/Os

EP1810LC-25T Applications

There are a lot of Altera
EP1810LC-25T FPGAs applications.

Voice recognition
Cryptography
Filtering and communication encoding
Aerospace and Defense
Medical Electronics
Audio
Automotive
Consumer Electronics
Distributed Monetary Systems
Data Center

User Guide

PURCHASE

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MEANS OF PAYMENT

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IMPORTANT NOTICE

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Step2：Desiccant Protection

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Step6：Packaging Box

SHIPPING COST

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2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.

SHIPPING METHOD

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.