Microchip EEC1005-I/WC-UB1
Manufacturer No:
EEC1005-I/WC-UB1
Manufacturer:
Microchip
Package:
Description:
Enterprise Storage Backplane Management Processor
Quantity:
In Stock :9865
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EEC1005-I/WC-UB1 Information
Microchip EEC1005-I/WC-UB1 technical specifications, attributes, parameters and parts with similar specifications to Microchip EEC1005-I/WC-UB1.
- Type
- Parameter
- Part Family
- EEC
- CPU Type
- Cortex-M4
- MaxSpeed (MHz)
- 48
- Program Memory Size (KB)
- 0
- SRAM (KB)
- 250
- Temp. Range Min.
- -40
- Temp. Range Max.
- 85
- Operation Voltage Min.(V)
- 1.62
- Operation Voltage Max.(V)
- 3.6
- SPI
- 0
- Type
- Parameter
- I2C
- 5
- UART
- 3
- QSPI
- 2
- Crypto Engine
- Yes
- Pin Count
- 144
- Secure Boot
- No
Download datasheets and manufacturer documentation for Microchip EEC1005-I/WC-UB1.
Data Sheets:
Product Brief:
Brochures:
EEC1005-UB2 is a generic, easily configurable, True Universal Backplane Management (UBM) device that can be used on hard drive backplanes to provide complete storage enclosure management and reporting to computing host systems using industry standard communication protocols.
Family members are identified with a suffix of UB1 or UB2 in their ordering number, where UB1 represents the part originally ordered as simply EEC1005. UB2 devices incorporate enhancements in their functionality.
EEC1005-UB2 supports a variety of host interfaces to accommodate SAS/SATS/NVMe backplane. The SFF-8654 slimline connector (Host facing Connector) can be used to route SAS signals in which case the HBA will manage SAS/SATA drives, the same connector protocol (physically a different connector) can be used to route PCIe signals in which case the HBA will manage NVME drives. In both cases UBM will be used as management protocol with support of SGPIO as well on SAS Slimline (Configuration dependent).The device supports using U.2 and U.3 Drive facing Connectors. EEC1005-UB2 also supports Multiple Backplanes on a single chassis.
EEC1005-UB2 supports 2 or 3 LED IBPI blinking patterns for up to 16 drives. Customized LED blink pattern can also be programmed through the FRU.
The EEC1005-UB2 has a secure boot loader that authenticates and decrypts the Flash boot image (UBM application) using the AES-256, ECDSA P-256, SHA-256 cryptographic hardware accelerators. EEC1005-UB2 hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and EC_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Additionally, the device offers lockable OTP storage for private keys and IDs.
EEC1005-UB2 is available in 84 pin and 144 pin WFBGA packages.
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