Microchip DSPIC33FJ64GP706-I/PT
Manufacturer No:
DSPIC33FJ64GP706-I/PT
Manufacturer:
Microchip
Package:
64-TQFP
Description:
40 MIPS, 64KB Flash, 16KB RAM, 64 pins, CAN
Quantity:
In Stock :6814
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Expected Shipping：Thu, Jun 11 - Fri, Jun 12, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DSPIC33FJ64GP706-I/PT Information
Microchip DSPIC33FJ64GP706-I/PT technical specifications, attributes, parameters and parts with similar specifications to Microchip DSPIC33FJ64GP706-I/PT.
- Type
- Parameter
- CPU Type
- dsPIC® DSC
- CPU Speed Max MHz (megahertz)
- 40
- Program Memory Size (KB)
- 64
- Multiple Flash Panels
- False
- Direct Memory Access (DMA) Channels
- 8
- Temp. Range Min.(C°)
- -40
- Temp. Range Max.(C°)
- 85
- Operation Voltage Min.(V)
- 3
- Operation Voltage Max.(V)
- 3.6
- Pin Count
- 64
- Type
- Parameter
- Low Power
- No
- Number of Comparators
- 0
- ADC Modules
- 2
- ADC Channels
- 18
- ADC Resolution Max
- 12
- ADC Sampling Rate (ksps)
- 500
- Number of DACs
- 0
- DAC outputs
- 0
- Max DAC Resolution (bits)
- 0
- Hardware RTCC
- No
Download datasheets and manufacturer documentation for Microchip DSPIC33FJ64GP706-I/PT.
Reference Manual:
Supporting Collateral:
Programming Specifications:
Legacy Collaterals:
Data Sheets:
Application Notes:
dsPIC33F General Purpose Digital Signal Controller (DSC) with seamless migration options to PIC24F, PIC24H MCUs and dsPIC30F DSCs in similar packages.
- Operating Range: • DC – 40 MIPS (40 MIPS @ 3.0-3.6V, -40°C to +85°C) • Industrial temperature range (-40°C to +85°C) High-Performance DSC CPU: • Modified Harvard architecture • C compiler optimized instruction set • 16-bit wide data path • 24-bit wide instructions • Linear program memory addressing up to 4M instruction words • Linear data memory addressing up to 64 Kbytes • 83 base instructions: mostly 1 word/1 cycle • Sixteen 16-bit General Purpose Registers • Two 40-bit accumulators: - With rounding and saturation options • Flexible and powerful addressing modes: - Indirect, Modulo and Bit-Reversed • Software stack • 16 x 16 fractional/integer multiply operations • 32/16 and 16/16 divide operations • Single-cycle multiply and accumulate: - Accumulator write back for DSP operations - Dual data fetch • Up to ±16-bit shifts for up to 40-bit data Direct Memory Access (DMA): • 8-channel hardware DMA: • 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA Interrupt Controller: • 5-cycle latency • 118 interrupt vectors • Up to 67 available interrupt sources • Up to 5 external interrupts • 7 programmable priority levels • 5 processor exceptions Digital I/O: • Wake-up/Interrupt-on-Change on up to 24 pins • Output pins can drive from 3.0V to 3.6V • All digital input pins are 5V tolerant • 4 mA sink on all I/O pins System Management: • Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated PLL - Extremely low jitter PLL • Power-up Timer • Oscillator Start-up Timer/Stabilizer • Watchdog Timer with its own RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources Power Management: • On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep and Doze modes with fast wake-up Timers/Capture/Compare/PWM: • Timer/Counters, up to nine 16-bit timers: - Can pair up to make four 32-bit timers - 1 timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to 8 channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to 8 channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode Communication Modules: • 3-wire SPI (up to 2 modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™ (up to 2 modules): - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART (up to 2 modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS • Data Converter Interface (DCI) module: - Codec interface - Supports I2S and AC’97 protocols - Up to 16-bit data words, up to 16 words per frame - 4-word deep TX and RX buffers • Enhanced CAN (ECAN™ module) 2.0B active (up to 2 modules): - Up to 8 transmit and up to 32 receive buffers - 16 receive filters and 3 masks - Loopback, Listen Only and Listen All Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNet™ addressing support Analog-to-Digital Converters (ADCs): • Up to two ADC modules in a device • 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - 2, 4 or 8 simultaneous samples - Up to 32 input channels with auto-scanning - Conversion start can be manual or synchronized with 1 of 4 trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity CMOS Flash Technology: • Low-power, high-speed Flash technology • Fully static design • 3.3V (±10%) operating voltage • Industrial temperature • Low-power consumption
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