




Microchip DSPIC33FJ12MC202-I/SO
Manufacturer No:
DSPIC33FJ12MC202-I/SO
Manufacturer:
Package:
28-SOIC (0.295, 7.50mm Width)
Description:
40 MIPS, 12KB Flash, 1KB RAM, 28 pins, Motor Control
Quantity:
Delivery:




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In Stock :Available
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DSPIC33FJ12MC202-I/SO information
Microchip DSPIC33FJ12MC202-I/SO technical specifications, attributes, parameters and parts with similar specifications to Microchip DSPIC33FJ12MC202-I/SO.
- Type
- Parameter
- CPU Type
- dsPIC® DSC
- CPU Speed Max MHz (megahertz)
- 40
- Program Memory Size (KB)
- 12
- Multiple Flash Panels
- False
- Direct Memory Access (DMA) Channels
- 0
- Temp. Range Min.(C°)
- -40
- Temp. Range Max.(C°)
- 125
- Operation Voltage Min.(V)
- 3
- Operation Voltage Max.(V)
- 3.6
- Pin Count
- 28
- Low Power
- No
- Number of Comparators
- 0
- ADC Modules
- 1
- ADC Channels
- 6
- ADC Resolution Max
- 12
- ADC Sampling Rate (ksps)
- 1100
- Number of DACs
- 0
- DAC outputs
- 0
- Max DAC Resolution (bits)
- 0
- Hardware RTCC
- No
- Motor Control PWM Channels
- 8
- SMPS PWM Channels
- 0
- Number of PWM Time Bases
- 2
- Output Compare Channels
- 4
- Number of CAN Modules
- 0
- Type of CAN module Max
- None
- Crypto Engine
- No
- Quadrature Encoder Interface (QEI)
- 1
- Segment LCD
- 0
- LCD/Graphics Interface
- No
- Configurable Logic Cell Modules (CLC /CCL)
- 0
- Peripheral Pin Select (PPS)/Pin Muxing
- Yes
Download datasheets and manufacturer documentation for Microchip DSPIC33FJ12MC202-I/SO.
Application Notes:
Reference Manual:
Supporting Collateral:
Programming Specifications:
Legacy Collaterals:
Data Sheets:
Miscellaneous:
- Operating Range:
- Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
- High-Performance DSC CPU:
- Modified Harvard architecture
- C compiler optimized instruction set
- 16-bit-wide data path
- 24-bit-wide instructions
- Linear program memory addressing up to 4M instruction words
- Linear data memory addressing up to 64 Kbytes
- 83 base instructions: mostly one word/one cycle
- Two 40-bit accumulators with rounding and saturation options
- Flexible and powerful addressing modes:
- Software stack
- 16 x 16 fractional/integer multiply operations
- 32/16 and 16/16 divide operations
- Single-cycle multiply and accumulate: Up to ±16-bit shifts for up to 40-bit data
- Timers/Capture/Compare/PWM:
- Timer/Counters, up to three 16-bit timers
- Input Capture (up to four channels)
- Output Compare (up to two channels)
- Interrupt Controller:
- 5-cycle latency
- Up to 26 available interrupt sources
- Up to three external interrupts
- Seven programmable priority levels
- Four processor exceptions
- Digital I/O:
- Peripheral pin Select functionality
- Up to 21 programmable digital I/O pins
- Wake-up/Interrupt-on-Change for up to 21 pins
- Output pins can drive from 3.0V to 3.6V
- Up to 5V output with open drain configurations on 5V tolerant pins
- 4 mA sink on all I/O pins
- On-Chip Flash and SRAM:
- Flash program memory (12 Kbytes)
- Data SRAM (1024 bytes)
- Boot and General Security for program Flash System Management:
- Flexible clock option
- Power-up Timer
- Oscillator Start-up Timer/Stabilizer
- Watchdog Timer with its own RC oscillator
- Fail-Safe Clock Monitor
- Reset by multiple sources
- Power Management:
- On-chip 2.5V voltage regulator
- Switch between clock sources in real time
- Idle, Sleep, and Doze modes with fast wake
- Motor Control Peripherals:
- 6-channel 16-bit Motor Control PWM
- Quadrature Encoder Interface module
- Analog-to-Digital Converters (ADCs):
- 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- -Two and four simultaneous samples (10-bit ADC)
- -Up to six input channels with auto-scanning
- CMOS Flash Technology:
- Low-power, high-speed Flash technology
- Fully static design
- 3.3V (±10%) operating voltage
- Industrial and Extended temperature
- Low power consumption
- Communication Modules:
- 4-wire SPI:
- -Framing supports I/O interface to simple codecs
- - Supports 8-bit and 16-bit data
- -Supports all serial clock formats and sampling modes
- I2C™:
- - Full Multi-Master Slave mode support
- - 7-bit and 10-bit addressing
- - Bus collision detection and arbitration
- - Integrated signal conditioning
- - Slave address masking
- UART:
- - Interrupt on address bit detect
- - Interrupt on UART error
- - Wake-up on Start bit from Sleep mode
- - 4-character TX and RX FIFO buffers
- - LIN bus support
- - IrDA® encoding and decoding in hardware
- - High-Speed Baud mode
- - Hardware Flow Control with CTS and RTS
User Guide
Please verify all part numbers, quantities, and packaging preferences before placing your order. If substitutions are acceptable, please indicate this clearly. For time-sensitive projects, confirm estimated delivery dates and stock availability in advance. Once submitted, changes or cancellations may not be possible, especially for items marked as non-cancellable/non-returnable (NCNR). For international shipments, please ensure all import documentation is complete and accurate to avoid delays.
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Quotations are subject to stock availability and may vary with market conditions. Prices and lead times are not guaranteed until a purchase order is confirmed. Ensure your contact details are correct to avoid delays in response.

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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
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