Microchip DSPIC33AK512MC510T-I/PT
Manufacturer No:
DSPIC33AK512MC510T-I/PT
Manufacturer:
Microchip
Package:
Description:
200 MHz 32-bit Single-Core Digital Signal Controller (DSC) designed for motor control, digital power, advanced sensing and touch
Quantity:
In Stock :1759
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Expected Shipping：Thu, May 28 - Fri, May 29, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DSPIC33AK512MC510T-I/PT Information
Microchip DSPIC33AK512MC510T-I/PT technical specifications, attributes, parameters and parts with similar specifications to Microchip DSPIC33AK512MC510T-I/PT.
- Type
- Parameter
- Family
- 32-bit DSC
- CPU Speed Max MHz (megahertz)
- 200
- FPU
- Yes
- Operation Voltage Max.(V)
- 3.6
- Operation Voltage Min.(V)
- 3.0
- TempRange Max
- +150
- TempRange Min
- -40
- Program Memory size (KB)
- 512
- RAM KB (kilobyte)
- 64
- Multiple Flash Panels
- yes
- Type
- Parameter
- Windowed Watch Dog Timer (WWDT)
- Yes
- Peripheral Pin Select / Pin Muxing
- Yes
- Peripheral Trigger Generator
- 1
- Pincount
- 100
- Configurable Logic Cell (CLC/CCL)
- 10
- CRC
- Yes
- Direct Memory Access (DMA) Channels
- 8
- ADC Channels
- 26
- ADC Resolution (bits)
- 12
- ADC Sample/Hold
- 5
Download datasheets and manufacturer documentation for Microchip DSPIC33AK512MC510T-I/PT.
Tech Brief:
Data Sheets:
Application Notes:
Programming Specification:
Reference Manuals:
Migration Guides:
200MHz, 32-bit dsPIC33A Digital Signal Controller (DSC) with 32/64bit Floating-Point Unit (FPU) and up to 512KB Flash Program Memory and 64KB SRAM Data Memory. High-speed 40MSPS 12-bit ADCs, high-bandwidth 100MHz op amps with low input voltage offset, fast 5nS comparators and high-speed PWM outputs designed to optimize real-time control applications. Designed as per ISO 26262 and IEC 61508 Functional Safety Compliance, the family offers on-chip security features and AEC-Q100 qualification support.
- Operating Conditions
- 3.0V to 3.6V: -40°C to +85°C, DC to 200 MHz
- 3.0V to 3.6V: -40°C to +125°C, DC to 200 MHz
- 3.0V to 3.6V: -40°C to +150°C, DC to 100 MHz
- High-Performance dsPIC33A Digital Signal Controller (DSC)
- 32-bit Rich Instruction Set for Optimized Speed and Program Code Size
- Non-paged linear Data/Flash 24-bit addressing space
- 16-bit/32-bit instructions for optimized code size and performance
- 32-bit Wide Data Paths
- Single and Double Precision Floating-Point Unit (FPU) Coprocessor
- Edge or Level Change Notification Interrupt on I/O pins
- Peripheral Pin Select (PPS) Remappable Pins to Reduce Board Layout Complexity
- Multiple Interrupt Vectors with Individual Programmable Priority
- Five External Interrupt Pins
- Selectable Oscillator Options Including:
- 8 MHz, 1% at 0ºC-85ºC Internal Fast RC (FRC) oscillator
- 8 MHz, 2% Internal Backup Fast RC (BFRC) oscillator with 32 kHz divided output
- 2 Kbyte Instruction Cache
- Sixteen 32-bit Working Registers
- Dual 72-bit Accumulators Supporting 32-bit and 16-bit Fixed-Point DSP Operations
- Eight Level Deep Working Register Sets
- Eight Level Deep Accumulator Register Sets
- Eight Level Deep Floating Point Register Sets
- Memory Features
- Up to 512 Kbytes of Program Flash Memory:
- 10,000 erase/write cycle endurance
- 20 years minimum data retention
- Self-programmable under software control
- Programmable code protection
- Flash Error Correcting Code (ECC)
- Programmable OTP regions
- Entire Flash OTP by ICSP™ write inhibit
- High-speed crystal resonator oscillator or external clock
- Up to 64 Kbytes of RAM Memory:
- 8-channel hardware Direct Memory Access (DMA) module
- RAM Error Correcting Code (ECC)
- RAM Memory Built-In Self-Test (MBIST)
- Flash Built-In Self-Test (NVMBIST)
- High-Speed PWM
- Multiple PWM Generators:
- Twelve pair (twenty four output) generators with resolution down to 1.25 ns
- Dead-Time Compensation Supports Lower Speed Operation
- PWM Support for:
- BLDC, PMSM, ACIM, SRM and stepper motors
- Constant on-time, hysteretic, burst mode power applications
- Fault and Current Limit Inputs
- Flexible Trigger Configuration for ADC Triggering
- High-Speed Analog-to-Digital Converters
- Five 12-bit Resolution ADCs
- Up to 40 MSPS Conversion Rate
- Up to 26 Analog Input Pins
- Sixteen Settings Channels. Each Channel:
- Can be assigned to any analog input (I/O pin or internal signal)
- Can be set to a different sampling time
- Can be configured as single-ended or differential
- Conversion result can be formatted as unsigned or signed
- Conversion result can be left-aligned (fraction format)
- Has a separate 32-bit conversion result register
- Supports Four Sampling modes:
- Oversampling of multiple samples
- Integration of multiple samples
- Window (multiple samples accumulated when the gate signal is active)
- Single Conversion
- All channels have a digital comparator to detect when the conversion result is less than, greater than, in bounds or out of bounds for the configurable thresholds
- Last three settings channels have the second result accumulator to implement second order filters
- Band Gap Reference and Temperature Sensor Diode Inputs
- Other Analog Features
- Eight 5 nS Analog Comparators with 12-bit PDM DACs
- Input multiplexing
- Slope compensation
- Up to two DAC output buffers
- Four Constant-Current Sources
- 3 Rail-to-Rail 100 MHz Operational Amplifiers with 40 V/μS slew rate
- 1 mV offset (typical) with calibration of input offset voltage
- Integrated Touch Controller:
- Independent from ADC processing capability
- Self and Mutual CVD Touch Modes support
- 18 TO 32 Touch ADC RX inputs
- 8 TO 32 Touch TX outputs
- Advanced capacitive sensing, touch buttons, sliders and wheels
- Up to 32 self-capacitance channels and up to 256 mutual-capacitance channels
- Peripheral Features
- Four 4-Wire SPI Modules:
- 32-byte FIFO
- Variable data width
- I2S mode
- Three I2C Modules w/Address Masking and IPMI Support
- Three Protocol UARTs with 8-bit RX/TX FIFOs and Automated Handling Support for:
- LIN 2.2
- DMX
- Smart card (ISO 7816)
- IrDA®
- Two SENT Modules
- Three Dedicated 32-bit Timer/Counter
- Single (SCCP) and Multiple (MCCP) Output Capture/Compare/PWM/Timer Modules:
- One MCCP Module
- Eight SCCP Modules
- Flexible configuration as PWM, input capture, output compare or timers
- Two 16-bit timers or one 32-bit timer in each module
- Single PWM output pin
- Four Quadrature Encoder Interface (QEI):
- Four inputs: Phase A, Phase B, Home, Index
- Ten Configurable Logic Cells (CLC) with Internal Connections to Select Peripherals and PPS
- Serial Encoder Interface BiSS with up to Four Client Encoders Support
- Peripheral Trigger Generator (PTG):
- 14 input trigger sources from other peripheral modules
- 5 output triggers to other peripheral modules
- 4 individual interrupt request signals
- CPU independent state machine-based instruction sequencer
- Security Module
- Flash OTP by ICSP Write Inhibit
- On-chip Secure Boot Flash Configurable as an Immutable Root-of-Trust
- Secure Boot Support: Validation of Host Code Image and Host Code Signature Validation
- Secure Update Support for Host Code: Secure Encryption Key Storage and Image Decryption
- X.509 Certification Storage, Parsing, Validation and Revocation, Supporting both ECC and RSA
- 128-bit Unique Device Serial Number for Identification (UUID)
- Support for Secure Use Cases:
- Secure Boot
- Secure FW upgrade
- Secure debug
- Device locking
- Key Storage in IRT/ Immutable secure boot region for realizing: secure boot, secure firmware update, secure debug
- Flash protection:
- Configuration of up to 8 Flash protection regions across ranges of Flash addresses
- Regions can be configured as: Immutable Root-of-Trust (IRT), OTP region, combination of R/W/X protections.
- Regions can be: Made permanent, locked until device reset, enabled/disabled during code execution
- Safety Features
- Windowed Watchdog Timer (WDT)
- Deadman Timer (DMT)
- Sixteen I/O Integrity Monitors (IOIM)
- Fail-Safe Clock Monitor (FSCM) with Automatic Switchover to Backup Clock Source with:
- Programmable over-frequency/under-frequency thresholds
- Flash Error Correcting Code (ECC)
- RAM Error Correcting Code (ECC)
- RAM Memory Built-In Self-Test (MBIST)
- 32-bit Cyclic Redundancy Check (CRC) Module
- Entire Flash OTP by ICSP™ Write Inhibit
- Capless Internal Voltage Regulator
- Virtual PPS Pins for Redundancy and Monitoring
- Temperature Sensor Diode
- Functional Safety
- ISO 26262 and IEC 61508 Compliant Device Development
- Functional Safety Support – ISO 26262/IEC 61508/IEC 60730. To learn about the Functional Safety Support of this device family and various Functional Safety standards an application can target using this device family
- Qualification
- AEC-Q100 REV H: Grade 1: -40°C to +125°C
- AEC-Q100 REV H: Grade 0: -40°C to +150°C
- Programming and Debug Interfaces
- Three Programming and Debugging Interfaces:
- Two-wire ICSP™ interface with non-intrusive access and real-time data exchange with application
- Five Program Addresses and Five Full-Featured Breakpoints
- IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan
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