Microchip DSPIC30F2012-20I/ML
Manufacturer No:
DSPIC30F2012-20I/ML
Manufacturer:
Microchip
Package:
28-VQFN Exposed Pad
Description:
30 MIPS, 12KB Flash, 1KB RAM, 28 pins
Quantity:
In Stock :6217
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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User Guide
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
DSPIC30F2012-20I/ML Information
Microchip DSPIC30F2012-20I/ML technical specifications, attributes, parameters and parts with similar specifications to Microchip DSPIC30F2012-20I/ML.
- Type
- Parameter
- CPU Type
- dsPIC® DSC
- CPU Speed Max MHz (megahertz)
- 30
- Program Memory Size (KB)
- 12
- Multiple Flash Panels
- No
- Direct Memory Access (DMA) Channels
- 0
- Temp. Range Min.(C°)
- -40
- Temp. Range Max.(C°)
- 125
- Operation Voltage Min.(V)
- 2.5
- Operation Voltage Max.(V)
- 5.5
- Pin Count
- 28
- Type
- Parameter
- Low Power
- No
- Number of Comparators
- 0
- ADC Modules
- 1
- ADC Channels
- 10
- ADC Resolution Max
- 12
- ADC Sampling Rate (ksps)
- 200
- Number of DACs
- 0
- DAC outputs
- 0
- Max DAC Resolution (bits)
- 0
- Hardware RTCC
- No
Download datasheets and manufacturer documentation for Microchip DSPIC30F2012-20I/ML.
Application Notes:
Errata:
Reference Manual:
User Guide:
Legacy Collaterals:
Supporting Collateral:
Data Sheets:
Programming Specifications:
dsPIC30F Sensor Family 16-bit Digital Signal Controller
- High-Performance dsPIC30F core
- Modified Harvard architecture
- C compiler optimized instruction set architecture
- 24-bit wide instructions, 16-bit wide data path
- Up to 30 MIPS operation
- DSP Engine for math intensive operations
- Modulo and Bit-Reversed Addressing modes
- Two, 40-bit wide accumulators with optional saturation logic
- 17-bit x 17-bit single cycle hardware fractional/ integer multiplier
- Single cycle Multiply-Accumulate (MAC) operation
- 40-stage Barrel Shifter
- Dual data fetch
- Operating Conditions
- Wide operating voltage range (2.5V to 5.5V)
- Industrial and Extended temperature ranges
- Peripheral Features
- High current sink/source I/O pins: 25 mA/25 mA
- Optionally pair up 16-bit timers into 32-bit timer modules
- 3-wire SPI™ modules (supports 4 Frame modes)
- I2C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing
- Addressable UART modules with FIFO buffers and selectable pins
- Analog Features
- 12-bit 200 Ksps Analog-to-Digital Converter (A/D)
- A/D Conversion available during Sleep and Idle
- 1 Sample/Hold
- Multiple Conversion Sequencing Options
- Special Microcontroller Features
- Enhanced Flash program memory with 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical)
- Data EEPROM memory with 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)
- Self-reprogrammable under software control
- Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
- Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation
- Fail-Safe clock monitor operation
- Detects clock failure and switches to on-chip low power RC oscillator
- Programmable code protection
- In-Circuit Serial Programming™ (ICSP™)
- Programmable Brown-out Detection and Reset generation
- DC to 40 MHz external clock input
- Internal FRC input with PLL active (4x, 8x, 16x)
- 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)
- 10 MHz - 20 MHz oscillator input in HS/2 or HS/3 with PLL active (4x, 8x, 16x)
- Sleep, Idle and Alternate Clock modes for power management
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