NXP DSP56F827FG80E
Manufacturer No:
DSP56F827FG80E
Manufacturer:
Package:
128-LQFP
Description:
128KB 64K x 16 FLASH 56800 16-Bit Microcontroller 56F8xx Series DSP56F827 2.5V 128-LQFP
Quantity:
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DSP56F827FG80E Information
NXP DSP56F827FG80E technical specifications, attributes, parameters and parts with similar specifications to NXP DSP56F827FG80E.
- Type
- Parameter
- Factory Lead Time
- 10 Weeks
- Mounting Type
- Surface Mount
- Package / Case
- 128-LQFP
- Surface Mount
- YES
- Operating Temperature
- -40°C~85°C TA
- Packaging
- Tray
- Series
- 56F8xx
- Published
- 1998
- JESD-609 Code
- e3
- Part Status
- Not For New Designs
- Type
- Parameter
- Moisture Sensitivity Level (MSL)
- 3 (168 Hours)
- Number of Terminations
- 128
- ECCN Code
- 3A991.A.2
- Terminal Finish
- Matte Tin (Sn)
- Additional Feature
- ALSO REQUIRES 3.3V SUPPLY
- HTS Code
- 8542.31.00.01
- Technology
- CMOS
- Terminal Position
- QUAD
- Terminal Form
- GULL WING
- Peak Reflow Temperature (Cel)
- 260
Download datasheets and manufacturer documentation for NXP DSP56F827FG80E.
Datasheets:
Environmental Information:
DSP56F827FG80E Description
The 56F827 is a member of the 56800 core-based families of controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F827 is well-suited for many applications. The 56F827 includes many peripherals that are especially useful for applications such as noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, and telephony.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable the rapid development of optimized control applications. The 56F827 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also provides two external dedicated interrupt lines, and up to 64 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
DSP56F827FG80E Features
Efficient 16-bit 56800 family processor engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE Debug Programming Interface
DSP56F827FG80E Relevant information
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