Texas Instruments DRA797BHGCBDRQ1
Manufacturer No:
DRA797BHGCBDRQ1
Manufacturer:
Texas Instruments
Package:
Description:
800 MHz Arm Cortex-A15 SoC processor w/ 750 MHz C66x DSP for audio amplifier
Quantity:
In Stock :6607
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Shipped from：HK Warehouse
Expected Shipping：Thu, May 28 - Fri, May 29, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DRA797BHGCBDRQ1 Information
Texas Instruments DRA797BHGCBDRQ1 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments DRA797BHGCBDRQ1.
- Type
- Parameter
- CPU
- 1 Arm Cortex-A15
- Frequency (MHz)
- 800
- Coprocessors
- 2 Dual Arm Cortex-M4
- Display type
- 1 HDMI, 2 LCD
- Protocols
- Ethernet, ICSS, Profibus
- Ethernet MAC
- 1-Port 10/100/1000, 2-Port 1Gb switch
- PCIe
- 2 PCIe Gen 2
- Hardware accelerators
- Audio tracking logic, Viterbi decoder
- Features
- Multimedia
- Operating system
- Android, Linux, RTOS
- Type
- Parameter
- Security
- Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection
- Rating
- Automotive
- Operating temperature range (°C)
- -40 to 125
- Package
- FCCSP (CBD)
- Pins
- 538
- Size
- 289 mm² 17 x 17
- REACH Status
- Yes
- RoHS Status
- RoHS Compliant
Download datasheets and manufacturer documentation for Texas Instruments DRA797BHGCBDRQ1.
User guide:
EVM User's guide:
Data sheet:
Application note:
The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The DRA79x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.
The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.
The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The DRA79x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.
The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.
- Architecture designed for infotainment co-processor applications, hybrid radio and amplifier applications
- Arm® Cortex®-A15 microprocessor subsystem
- C66x floating-point VLIW DSP
- Fully object-code compatible with C67x and C64x+
- Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
- Up to 512KB of on-chip L3 RAM
- Level 3 (L3) and Level 4 (L4) interconnects
- DDR3/DDR3L Memory Interface (EMIF) module
- Supports up to DDR-1333 (667 MHz)
- Up to 2GB across single chip select
- Dual Arm® Cortex®-M4 Image Processing Units (IPU)
- Display subsystem
- Display controller With DMA engine and up to three pipelines
- HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
- Video Processing Engine (VPE)
- One Video Input Port (VIP) module
- Support for up to four multiplexed input ports
- General-Purpose Memory Controller (GPMC)
- Enhanced Direct Memory Access (EDMA) controller
- 2-port gigabit ethernet (GMAC)
- Up to two external ports
- Sixteen 32-bit general-purpose timers
- 32-Bit MPU watchdog timer
- Six high-speed inter-integrated circuit (I2C) ports
- HDQ™/1-Wire® Interface
- Ten configurable UART/IrDA/CIR modules
- Four Multichannel Serial Peripheral Interfaces (McSPI)
- Quad SPI Interface (QSPI)
- Media Local Bus Subsystem (MLBSS)
- Eight Multichannel Audio Serial Port (McASP) modules
- SuperSpeed USB 3.0 dual-role device
- High-speed USB 2.0 dual-role device
- High-speed USB 2.0 on-the-go
- Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
- PCI Express® 3.0 subsystems with two 5-Gbps lanes
- One 2-lane Gen2-compliant port
- or two 1-lane Gen2-compliant ports
- Dual Controller Area Network (DCAN) modules
- CAN 2.0B protocol
- MIPI® CSI-2 camera serial interface
- Up to 186 General-Purpose I/O (GPIO) pins
- Device security features
- Hardware crypto accelerators and DMA
- Firewalls
- JTAG lock
- Secure keys
- Secure ROM and boot
- Customer programmable keys
- Power, reset, and clock management
- On-chip debug with CTools technology
- 28-nm CMOS technology
- 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)
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