Texas Instruments CY74FCT273ATQCTG4
Texas Instruments CY74FCT273ATQCTG4

Texas Instruments CY74FCT273ATQCTG4

Manufacturer No:

CY74FCT273ATQCTG4

Manufacturer:

Texas Instruments

Package:

Description:

Octal D-Type Flip-Flops with Clear

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In Stock :5503

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Shipped from:HK Warehouse
Expected Shipping:Tue, May 12 - Wed, May 13, 2026
Date Code:Within 2 Years

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Step1:Prepare product

Step1:Prepare product

Step2:Desiccant Protection

Step2:Desiccant Protection

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Step3:Vacuum Packaging

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Step4:Individual Package

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Step5:Anti-collision Filling

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Step6:Packaging Box

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SHIPPING METHOD

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.

CY74FCT273ATQCTG4 Information

Texas Instruments CY74FCT273ATQCTG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments CY74FCT273ATQCTG4.

  • Type
  • Parameter
  • Number of channels
  • 8
  • Technology family
  • FCT
  • Supply voltage (min) (V)
  • 4.75
  • Supply voltage (max) (V)
  • 5.25
  • Input type
  • TTL, TTL-Compatible CMOS
  • Output type
  • CMOS, Push-Pull
  • Clock frequency (max) (MHz)
  • 100
  • IOL (max) (mA)
  • 64
  • IOH (max) (mA)
  • -32
  • Supply current (max) (µA)
  • 200
  • Type
  • Parameter
  • Features
  • Partial power down (Ioff), Very high speed (tpd 5-10ns)
  • Operating temperature range (°C)
  • -40 to 85
  • Rating
  • Catalog
  • Package
  • SOIC (DW)
  • Pins
  • 20
  • Size
  • 131.84 mm² 12.8 x 10.3
  • Package
  • SSOP (DBQ)
  • Pins
  • 20
  • Size
  • 51.9 mm² 8.65 x 6
  • REACH Status
  • Yes

The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • CY54FCT273T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT273T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current