Renesas CD4099BKMSR

Manufacturer No:

CD4099BKMSR

Manufacturer:

Renesas

Package:

Description:

CMOS 8-Bit Addressable Latch

Quantity:

In Stock :3684

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Shipped from：HK Warehouse

Expected Shipping：Thu, May 7 - Fri, May 8, 2026

Lead Time：Inquire about availability

Date Code：Within 2 Years

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Step1：Prepare product

Step2：Desiccant Protection

Step3：Vacuum Packaging

Step4：Individual Package

Step5：Anti-collision Filling

Step6：Packaging Box

SHIPPING COST

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SHIPPING METHOD

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.

CD4099BKMSR Information

Renesas CD4099BKMSR technical specifications, attributes, parameters and parts with similar specifications to Renesas CD4099BKMSR.

Type
Parameter

Pkg. Type
CFP

Lead Count (#)
16

Carrier Type
Tray

Moisture Sensitivity Level (MSL)
Not Applicable

Pitch (mm)
1.3

Pkg. Dimensions (mm)
10.4 x 6.9 x 0.00

DLA SMD
5962R9661501VXC

Pb (Lead) Free
Exempt

Pb Free Category
Gold Plate over compliant Undercoat-e4

Type
Parameter

Temp. Range
-55 to +125°C

DSEE (MeV·cm2/mg)
75

Length (mm)
10.4

Qualification Level
QML Class V (space)

Rating
Space

TID HDR (krad(Si))
100

TID LDR (krad(Si))
ELDRS free

Thickness (mm)
0

Width (mm)
6.9

Moisture Sensitivity Level (MSL)
Not Applicable

Download datasheets and manufacturer documentation for Renesas CD4099BKMSR.

The CD4099BMS 8-bit addressable latch is a serial input, parallel output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic 0 level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1 of 8 demultiplexer; the bit that is addressed has an active output that follows the data input, while all unaddressed bits are held to a logic 0 level. The CD4099BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4X, Frit Seal DIP H1F, Ceramic Flatpack H6W.

High-voltage type (20V rating)
Serial data input
Active parallel output
Storage register capability
Master clear
Can function as demultiplexer
100% tested for quiescent current at 20V
5V, 10V and 15V parametric ratings
Standardized symmetrical output characteristics
Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
Noise margin (over full package temperature range) 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
Meets All Requirements of JEDEC tentative standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"