Renesas CD4099BDMSR
Manufacturer No:
CD4099BDMSR
Manufacturer:
Renesas
Package:
Description:
CMOS 8-Bit Addressable Latch
Quantity:
In Stock :9115
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
CD4099BDMSR Information
Renesas CD4099BDMSR technical specifications, attributes, parameters and parts with similar specifications to Renesas CD4099BDMSR.
- Type
- Parameter
- Pkg. Type
- SBDIP
- Lead Count (#)
- 16
- Carrier Type
- Tube
- Moisture Sensitivity Level (MSL)
- Not Applicable
- Pitch (mm)
- 2.5
- Pkg. Dimensions (mm)
- 20.3 x 7.5 x 2.41
- DLA SMD
- 5962R9661501VEC
- Pb (Lead) Free
- Exempt
- Pb Free Category
- Gold Plate over compliant Undercoat-e4
- MOQ
- 25
- Type
- Parameter
- Temp. Range
- -55 to +125°C
- DSEE (MeV·cm2/mg)
- 75
- Length (mm)
- 20.3
- Qualification Level
- QML Class V (space)
- Rating
- Space
- TID HDR (krad(Si))
- 100
- TID LDR (krad(Si))
- ELDRS free
- Thickness (mm)
- 2.41
- Width (mm)
- 7.5
- Moisture Sensitivity Level (MSL)
- Not Applicable
Download datasheets and manufacturer documentation for Renesas CD4099BDMSR.
The CD4099BMS 8-bit addressable latch is a serial input, parallel output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic 0 level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1 of 8 demultiplexer; the bit that is addressed has an active output that follows the data input, while all unaddressed bits are held to a logic 0 level. The CD4099BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4X, Frit Seal DIP H1F, Ceramic Flatpack H6W.
- High-voltage type (20V rating)
- Serial data input
- Active parallel output
- Storage register capability
- Master clear
- Can function as demultiplexer
- 100% tested for quiescent current at 20V
- 5V, 10V and 15V parametric ratings
- Standardized symmetrical output characteristics
- Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
- Noise margin (over full package temperature range) 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
- Meets All Requirements of JEDEC tentative standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
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