Renesas CD4027BKMSR
Manufacturer No:
CD4027BKMSR
Manufacturer:
Renesas
Package:
Description:
CMOS Dual J-K Master-Slave Flip-Flop
Quantity:
In Stock :1757
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
CD4027BKMSR Information
Renesas CD4027BKMSR technical specifications, attributes, parameters and parts with similar specifications to Renesas CD4027BKMSR.
- Type
- Parameter
- Pkg. Type
- CFP
- Lead Count (#)
- 16
- Carrier Type
- Tray
- Moisture Sensitivity Level (MSL)
- Not Applicable
- DLA SMD
- 5962R9662901VXC
- Pb (Lead) Free
- Exempt
- Pb Free Category
- Gold Plate over compliant Undercoat-e4
- MOQ
- 25
- Temp. Range
- -55 to +125°C
- DSEE (MeV·cm2/mg)
- 75
- Type
- Parameter
- Length (mm)
- 10.4
- Pitch (mm)
- 1.3
- Pkg. Dimensions (mm)
- 10.4 x 6.9 x 0.00
- Qualification Level
- QML Class V (space)
- Rating
- Space
- TID HDR (krad(Si))
- 100
- TID LDR (krad(Si))
- ELDRS free
- Thickness (mm)
- 0
- Width (mm)
- 6.9
- Moisture Sensitivity Level (MSL)
- Not Applicable
Download datasheets and manufacturer documentation for Renesas CD4027BKMSR.
The CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD4013B dual D-Type flip-flop. The CD4027BMS is useful in performing control, register and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high-level signal is present at either the Set or Reset input. The CD4027BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T, Frit Seal DIP H1E and Ceramic Flatpack H6W.
- High-voltage type (20V rating)
- Set - Reset capability
- Static flip-flop operation - Retains state indefinitely with clock level either "High" or "Low"
- Medium-speed operation - 16MHz (typ.) clock toggle rate at 10V
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20V
- Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
- Noise margin (over full package temperature range): 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
- 5V, 10V and 15V parametric ratings
- Meets all requirements of JEDEC tentative standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
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12.28 M
Listed Part Number
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In-stock SKU
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