Renesas CD4021BDMSR
Manufacturer No:
CD4021BDMSR
Manufacturer:
Renesas
Package:
Description:
CMOS 8-Stage Static Shift Register
Quantity:
In Stock :3931
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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CD4021BDMSR Information
Renesas CD4021BDMSR technical specifications, attributes, parameters and parts with similar specifications to Renesas CD4021BDMSR.
- Type
- Parameter
- Pkg. Type
- SBDIP
- Lead Count (#)
- 16
- Carrier Type
- Tube
- Moisture Sensitivity Level (MSL)
- Not Applicable
- Pitch (mm)
- 2.5
- Pkg. Dimensions (mm)
- 20.3 x 7.5 x 2.41
- DLA SMD
- 5962R9662302VEC
- Pb (Lead) Free
- Exempt
- Pb Free Category
- Gold Plate over compliant Undercoat-e4
- MOQ
- 25
- Type
- Parameter
- Temp. Range
- -55 to +125°C
- DSEE (MeV·cm2/mg)
- 75
- Length (mm)
- 20.3
- Qualification Level
- QML Class V (space)
- Rating
- Space
- TID HDR (krad(Si))
- 100
- TID LDR (krad(Si))
- ELDRS free
- Thickness (mm)
- 2.41
- Width (mm)
- 7.5
- Moisture Sensitivity Level (MSL)
- Not Applicable
Download datasheets and manufacturer documentation for Renesas CD4021BDMSR.
CD4014BMS - synchronous parallel or serial input/serial output CD4021BMS - asynchronous parallel input or synchronous serial input/serial output CD4014BMS and CD4021BMS series types are 8-stage parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel JAM inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, Q outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/ SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BMS, the CLOCK input of the internal stage is forced when an asynchronous parallel entry is made. Register expansion using multiple packages is permitted. The CD4014BMS and CD4021BMS are supplied in these 16-lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W
- High voltage types (20V rating)
- Medium speed operation 12MHz (Typ.) clock rate at VDD-VSS = 10V
- Fully static operation
- 8 master-slave flip-flops plus output buffering and control gating
- 100% tested for quiescent current at 20V
- Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
- Noise margin (full package temperature range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
- Standardized symmetrical output characteristics
- 5V, 10V and 15V parametric ratings
- Meets all requirements of JEDEC tentative standard No. 13B, "Standard Specifications for Description of "B" Series CMOS devices
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