Microchip ATSAM4S2AA-MU
Manufacturer No:
ATSAM4S2AA-MU
Manufacturer:
Microchip
Package:
48-VFQFN Exposed Pad
Description:
ATSAM4S2A
Quantity:
In Stock :4609
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Shipped from：HK Warehouse
Expected Shipping：Thu, May 28 - Fri, May 29, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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ATSAM4S2AA-MU Information
Microchip ATSAM4S2AA-MU technical specifications, attributes, parameters and parts with similar specifications to Microchip ATSAM4S2AA-MU.
- Type
- Parameter
- Part Family
- ATSAM4S2A
- CPU Type
- Cortex-M4
- MaxSpeed (MHz)
- 120
- Program Memory Size (KB)
- 128
- SRAM (KB)
- 64
- Temp. Range Min.
- -40
- Temp. Range Max.
- 85
- Operation Voltage Min.(V)
- 1.62
- Operation Voltage Max.(V)
- 3.6
- SPI
- 2
- Type
- Parameter
- I2C
- 2
- UART
- 3
- QSPI
- 0
- Crypto Engine
- No
- Internal Oscillator
- 4,8,12Mhz,32Khz
- Pin Count
- 48
Download datasheets and manufacturer documentation for Microchip ATSAM4S2AA-MU.
User Guide:
Application Notes:
Supporting Collateral:
Brochures:
Data Sheets:
Tech Brief:
Legacy Collaterals:
Microchip's ARM®-based SAM4S2A microcontroller builds on the high-performance 32-bit Cortex®-M4 core.
The SAM4S2A features:
- Maximum operating speed of 120MHz
- 128KB of flash memory and 64KB of SRAM
- 1.62V to 3.6V supply
- Power consumption of 180uA/MHz in dynamic mode, below 25uA in RAM retention mode and 1uA at 1.8V in back-up mode with the RTC running
- Extensive peripheral set for connectivity, system control and analog interfacing
- Native support for Microchip QTouch capacitive touch technology for implementation of buttons, sliders and wheels
- Pin-to-pin compatible with Microchip SAM7S, SAM3N, SAM4N and SAM3S MCUs
- Parallel Input/Output (IO) data capture mode
- ARM Cortex-M4 running at up to 120 MHz
- Memory Protection Unit (MPU)
- DSP Instructions,Thumb®-2 instruction set
- 128 Kbytes embedded Flash, ECC, Security Bit and Lock Bits
- 64 Kbytes embedded SRAM
- 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
- Embedded voltage regulator for single-supply operation
- Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for Safe Operation
- Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for RTT or system clock
- RTC with Gregorian and Persian Calendar Mode, Waveform Generation in Backup mode
- RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency inaccuracy
- High-precision 8/12 MHz factory-trimmed internal RC oscillator with 4 MHz default frequency for device startup, in-application trimming access for frequency adjustment
- Slow clock internal RC oscillator as permanent low-power mode device clock
- Two PLL up to 240 MHz for Device Clock and for USB
- Temperature Sensor
- Low-power tamper detection on two inputs, anti-tampering by immediate clear of general-purpose backup registers (GPBR)
- 22 Peripheral DMA Controllers
- Sleep, Wait and Backup modes; consumption down to 1 µA in Backup mode
- 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm
- 48-lead QFN, 7 x 7 mm, pitch 0.5 mm
- Revision A - Industrial (-40° C to +85° C), Revision B -(-40° C to +105° C)
- USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints, on-chip transceiver
- Up to two USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode
- Two 2-wire UARTs
- Up to two 2-Wire Interface modules (I2C-compatible), one SPI, one Serial Synchronous Controller (I2S)
- Two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode, Quadrature decoder logic and 2-bit Gray up/down counter for stepper motor
- 4-channel 16-bit PWM with complementary output, fault input, 12-bit dead time generator counter for motor control
- 32-bit Real-time Timer and RTC with calendar, alarm and 32 kHz trimming features
- 256-bit General Purpose Backup Registers (GPBR)
- 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) for data integrity check of off-/on-chip memories
- 34 I/O Lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die series resistor termination
- Three 32-bit Parallel Input/Output Controllers, Peripheral DMA-assisted Parallel Capture mode
- 8-channel, 1Msps ADC with differential input mode and programmable gain stage and auto calibration
- Serial Wire/JTAG Debug Port(SWJ-DP)
- Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.
- Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access.
- Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
- Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
- Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
- IEEE1149.1 JTAG Boundary-scan on all digital pins.
- ASF-Atmel software Framework – SAM software development framework
- Integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers.
- DMA support, Interrupt handlers Driver support
- USB, TCP/IP, Wi-Fi and Bluetooth, Numerous USB classes, DHCP and Wi-Fi encryption Stacks
- RTOS integration, FreeRTOS is a core component
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