Microchip ATSAM3U1EB-AU
Manufacturer No:
ATSAM3U1EB-AU
Manufacturer:
Microchip
Package:
144-LQFP
Description:
ATSAM3U1E
Quantity:
In Stock :6280
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Shipped from：HK Warehouse
Expected Shipping：Sat, May 30 - Sun, May 31, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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ATSAM3U1EB-AU Information
Microchip ATSAM3U1EB-AU technical specifications, attributes, parameters and parts with similar specifications to Microchip ATSAM3U1EB-AU.
- Type
- Parameter
- Part Family
- ATSAM3U1E
- CPU Type
- Cortex-M3
- MaxSpeed (MHz)
- 96
- Program Memory Size (KB)
- 64
- SRAM (KB)
- 20
- Temp. Range Min.
- -40
- Temp. Range Max.
- 85
- Operation Voltage Min.(V)
- 1.62
- Operation Voltage Max.(V)
- 3.6
- SPI
- 5
- Type
- Parameter
- I2C
- 2
- UART
- 5
- QSPI
- 0
- Crypto Engine
- No
- Internal Oscillator
- 4,8,12Mhz,32Khz
- Pin Count
- 144
Download datasheets and manufacturer documentation for Microchip ATSAM3U1EB-AU.
Legacy Collaterals:
Brochures:
Data Sheets:
Application Notes:
Supporting Collateral:
Microchip's ARM®-based SAM3U1E is a member of the SAM3U family of flash microcontrollers based on the high-performance 32-bit ARM Cortex®-M3 RISC processor.
It operates at a maximum speed of 96MHz and features 64KB of flash memory and 20KB of SRAM.
The peripheral set includes a High Speed USB device and PHY at 480Mbps, high-speed multimedia card interface for SDIO/SD/MMC, a 16-bit external bus interface supporting NAND flash, four USARTs, two TWIs (I2C), 5x SPIs, I2S, four PWM timers, three 16-bit timers, RTC, 8x12-bit and 8x10-bit ADC.
The architecture is designed to sustain high-speed data transfers. The multi-layer bus matrix, multiple SRAM banks, PDC, and DMA support parallel tasks and maximize data throughput.
The SAM3U1E operates from 1.62V to 3.6V and is available in 144-pin LQFP and BGA packages.
- ARM Cortex-M3 revision 2.0 running at up to 96 MHz
- Memory Protection Unit (MPU)
- Thumb®-2 instruction set
- 64 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank
- 20 Kbytes embedded SRAM
- 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
- Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash controller with 4 Kbytes RAM buffer and ECC
- External Bus Interface - 8 or 16 bits, 4 chip selects, 24-bit address
- Embedded voltage regulator for single-supply operation
- POR, BOD and Watchdog for safe reset
- Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock
- High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default Frequency for fast device startup
- Slow Clock Internal RC oscillator as permanent clock for device clock in low power mode
- One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Device
- 17 Peripheral DMA Controller (PDC) channels and 4-channel central DMA
- Sleep, Wait, and Backup modes, down to 1.65 μA in Backup mode with RTC, RTT, and GPBR
- 144-lead LQFP – 20 × 20 mm, pitch 0.5 mm
- 144-ball LFBGA – 10 × 10 mm, pitch 0.8 mm
- Industrial (-40° C to +85° C)
- USB 2.0 Device: 480 Mbps, 4-Kbyte FIFO, up to 7 bidirectional Endpoints, dedicated DMA
- 4 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester support) and one UART
- 2 TWI (I2C compatible)
- 1 Serial Perpheral Interface (SPI)
- 1 Synchronous Serial Controller (SSC) (I2S)
- 1 High Speed Multimedia Card Interface (HSMCI) (SDIO/SD/MMC)
- 3-channel 16-bit Timer/Counter (TC) for capture, compare and PWM
- 4-channel 16-bit PWM (PWMC)
- 32-bit Real-time Timer (RTT) and Real-time Clock (RTC) with calendar and alarm features
- 96 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination
- Three 32-bit Parallel Input/Output Controllers
- 8-channel 12-bit 1 msps ADC with differential input mode and programmable gain stage
- 8-channel 10-bit ADC
- Serial Wire/JTAG Debug Port(SWJ-DP)
- Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.
- Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access.
- Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
- Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
- Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
- IEEE1149.1 JTAG Boundary-scan on all digital pins.
- ASF-Atmel software Framework – SAM software development framework
- Integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers.
- DMA support, Interrupt handlers Driver support
- USB, TCP/IP, Wi-Fi and Bluetooth, Numerous USB classes, DHCP and Wi-Fi encryption Stacks
- RTOS integration, FreeRTOS is a core component
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