Microchip ATSAM3S4BA-MU
Manufacturer No:
ATSAM3S4BA-MU
Manufacturer:
Microchip
Package:
64-VFQFN Exposed Pad
Description:
ATSAM3S4B
Quantity:
In Stock :4683
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Shipped from：HK Warehouse
Expected Shipping：Thu, May 28 - Fri, May 29, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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ATSAM3S4BA-MU Information
Microchip ATSAM3S4BA-MU technical specifications, attributes, parameters and parts with similar specifications to Microchip ATSAM3S4BA-MU.
- Type
- Parameter
- Part Family
- ATSAM3S4B
- CPU Type
- Cortex-M3
- MaxSpeed (MHz)
- 64
- Program Memory Size (KB)
- 256
- SRAM (KB)
- 48
- Temp. Range Min.
- -40
- Temp. Range Max.
- 85
- Operation Voltage Min.(V)
- 1.62
- Operation Voltage Max.(V)
- 3.6
- SPI
- 3
- Type
- Parameter
- I2C
- 2
- UART
- 4
- QSPI
- 0
- Crypto Engine
- No
- Internal Oscillator
- 4,8,12Mhz,32Khz
- Pin Count
- 64
Download datasheets and manufacturer documentation for Microchip ATSAM3S4BA-MU.
Legacy Collaterals:
Data Sheets:
Brochures:
Application Notes:
Supporting Collateral:
The SAM3S4B is a member of the Microchip's SAM3S series microcontrollers based on the high-performance 32-bit ARM® Cortex®-M3 RISC processor. It operates at a maximum speed of 64MHz and features 256KB of flash memory and 48KB of SRAM.
The extensive peripheral set includes a Full Speed USB device port with embedded transceiver, a high-speed multimedia card interface for SDIO/SD/MMC, two USARTs, two UARTs, two TWIs (I2C), three SPIs, I2S, PWM timer, three 16-bit timers, RTC, 10-ch 12-bit ADC, 2-ch 12-bit DAC, and an analog comparator.
The QTouch library offers an easy way to implement buttons, wheels, and sliders. The parallel data capture mode on the PIOs collects data from external devices not compliant with standard memory read protocols, such as low-cost image sensors. DMA transfers the data to memory, offloading the CPU.
The device operates from 1.62V to 3.6V and is available in 64-pin QFP and QFN packages and is pin-to-pin compatible with the SAM3N4B and SAM7S64.
- ARM® Cortex®-M3 revision 2.0 running at up to 64 MHz
- Memory Protection Unit (MPU)
- DSP Instructions, Thumb®-2 instruction set
- 256 Kbytes Single Plane embedded Flash, 128-bit wide access, memory accelerator
- 48 Kbytes embedded SRAM
- 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
- Embedded voltage regulator for single-supply operation
- Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
- Quartz or ceramic resonator oscillators: 0.6 to 30MHz main power with Failure Detection and low power 32.768 kHz for RTC or device clock
- High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment
- Slow clock internal RC oscillator as permanent low-power mode device clock
- Two PLLs up to 130 MHz for device clock and for USB
- Temperature Sensor
- Up to 22 peripheral DMA (PDC) channels
- Sleep and Backup modes, down to < 2 μA in Backup mode
- Ultra low power RTC
- 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm
- 64-lead QFN, 9 x 9 mm, pitch 0.5 mm
- Industrial (-40° C to +85° C)
- USB 2.0 Device and Embedded Host: 12 Mbps, up to 8 bidirectional Endpoints and Multi-packet Ping-pong Mode. On-Chip Transceiver
- USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip Transceiver
- 2 USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode
- Two 2-wire UARTs
- 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller (I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)
- two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
- 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control
- 32-bit Real-time Timer and RTC with calendar and alarm features
- 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
- 47 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination
- Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel Capture Mode
- 10-channel, 1Msps ADC with differential input mode and programmable gain stage
- One 2-channel 12-bit 1Msps DAC
- One Analog Comparator with flexible input selection, Selectable input hysteresis
- Serial Wire/JTAG Debug Port(SWJ-DP)
- Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.
- Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access.
- Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
- Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
- Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
- IEEE1149.1 JTAG Boundary-scan on all digital pins.
- ASF-Atmel software Framework – SAM software development framework
- Integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers.
- DMA support, Interrupt handlers Driver support
- USB, TCP/IP, Wi-Fi and Bluetooth, Numerous USB classes, DHCP and Wi-Fi encryption Stacks
- RTOS integration, FreeRTOS is a core component
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