Microchip ATMEGA32A-MUR
Manufacturer No:
ATMEGA32A-MUR
Manufacturer:
Microchip
Package:
44-VFQFN Exposed Pad
Description:
ATmega32A
Quantity:
In Stock :4064
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Shipped from：HK Warehouse
Expected Shipping：Mon, Jun 1 - Tue, Jun 2, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
ATMEGA32A-MUR Information
Microchip ATMEGA32A-MUR technical specifications, attributes, parameters and parts with similar specifications to Microchip ATMEGA32A-MUR.
- Type
- Parameter
- Program Memory Size (KB)
- 32
- RAM
- 2048
- Data EEPROM (bytes)
- 1024
- Pin Count
- 44
- Operation Voltage Max.(V)
- 5.5
- Operation Voltage Min.(V)
- 2.7
- ADC Resolution Max
- 10
- ADC Channels
- 8
- Zero Cross Detect
- False
- Number of Comparators
- 1
- Type
- Parameter
- SPI
- 1
- I2C
- 1
- Stand alone PWM
- 4
- Low Power
- No
- Numerically Controlled Oscillator (NCO)
- 0
- Data Signal Modulator (DSM)
- 0
Download datasheets and manufacturer documentation for Microchip ATMEGA32A-MUR.
Supporting Collateral:
Reference Manual:
Application Notes:
Data Sheets:
The low-power, high-performance Microchip 8-bit AVR® RISC-based microcontroller featuring 32 KB self-programming Flash program memory, 2 KB SRAM, 1 KB EEPROM, 8-channel 10-bit A/D converter and JTAG interface for on-chip-debug. The device achieves 16 MIPS throughput at 16 MHz at 2.7-5.5V operation.
By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching one MIPS per MHz, allowing you to optimize power consumption versus processing speed.
- 131 Powerful Instructions - Most Single-clock Cycle Execution
- 32 × 8 General Purpose Working Registers
- Fully Static Operation
- Up to 16 MIPS Throughput at 16 MHz
- On-Chip Two-Cycle Multiplier
- 32 KB of In-System Self-programmable Flash program memory
- 1 KB EEPROM
- 2 KB Internal SRAM
- Write/Erase cycles: 10,000 Flash/100,000 EEPROM
- Data Retention: 20 years at 85°C/100 years at 25°C
- In-System Programming by On-chip Boot Program
- True Read-While-Write Operation
- Programming Lock for Software Security
- JTAG (IEEE std. 1149.1 Compliant) Interface
- Boundary-scan Capabilities According to the JTAG Standard
- Extensive On-chip Debug SupportProgramming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
- QTouch library support
- Capacitive touch buttons, sliders and wheels
- QTouch and QMatrix acquisition
- Up to 64 sense channels
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12.28 M
Listed Part Number
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