Texas Instruments AM62A32AMLHAAMB
Manufacturer No:
AM62A32AMLHAAMB
Manufacturer:
Texas Instruments
Package:
Description:
1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power, video surveillance, retail automation
Quantity:
In Stock :7517
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Date Code：Within 2 Years
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AM62A32AMLHAAMB Information
Texas Instruments AM62A32AMLHAAMB technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments AM62A32AMLHAAMB.
- Type
- Parameter
- Arm CPU
- 1 Arm Cortex-A53, 2 Arm Cortex-A53, 4 Arm Cortex-A53
- Coprocessors
- 1 Arm Cortex-R5F
- CPU
- 1 Arm Cortex-A53, 2 Arm Cortex-A53, 4 Arm Cortex-A53
- Display type
- MIPI DPI
- Protocols
- Ethernet, TSN
- Ethernet MAC
- 2-Port 10/100/1000
- Hardware accelerators
- Deep learning accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator
- Features
- Vision Analytics
- Operating system
- Linux, RTOS
- Security
- Secure boot
- Type
- Parameter
- Rating
- Catalog
- Power supply solution
- TPS65219
- Operating temperature range (°C)
- -40 to 125
- Package
- FCBGA (AMB)
- Pins
- 484
- Size
- 324 mm² 18 x 18
- Package
- FCCSP (ANF)
- Pins
- 484
- Size
- 324 mm² 18 x 18
- REACH Status
- Yes
Download datasheets and manufacturer documentation for Texas Instruments AM62A32AMLHAAMB.
Data sheet:
User guide:
Application note:
White paper:
Functional safety information:
Application brief:
Technical article:
AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, Robotics, and other markets. The cost optimized AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).
AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include the next generation C7000™ DSP from Texas Instruments (“C7x”) with scalar and vector cores, dedicated “MMA” deep learning accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.
The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and also employs advanced power management support for portable and power-sensitive applications.
Processor Cores:
- Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
- Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- 512KB SRAM with SECDED ECC
- Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- Deep Learning Accelerator based on Single-core C7x
- C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at 1.0GHz
- Matrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz
- 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
- 1.25MB of L2 SRAM with SECDED ECC
- Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
- 315MPixel/s ISP; Up to 5MP @ 60fps
- Support for 12-bit RGB-IR
- Support for up to 16-bit input RAW format
- Line support up to 4096
- Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
- Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL
Multimedia:
- Display subsystem
- Single display support
- Up to 2048x1080 @ 60fps
- Up to 165MHz pixel clock support with independent PLL
- DPI 24-bit RGB parallel interface
- Supports safety features such as freeze frame detection and MISR data check
- One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
- MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
- Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane
- ECC verification/correction with CRC check + ECC on RAM
- Virtual Channel support (up to 16)
- Ability to write stream data directly to DDR via DMA
- Video Encoder/Decoder
- Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
- Support for H.264 BaseLine/Main/High Profiles at Level 5.2
- Support for up to 4K UHD resolution (3840 × 2160)
- Clocking options supporting 240MPixels/s, 120MPixels/s, or 60MPixels/s
- Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)
Memory Subsystem:
- Up to 2.29MB of On-chip RAM
- 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
- 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
- 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
- 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
- 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
- 1.25MB of L2 SRAM with SECDED ECC in C7x Deep Learning Accelerator
- DDR Subsystem (DDRSS)
- Supports LPDDR4
- 32-bit data bus with inline ECC
- Supports speeds up to 3733MT/s
- Max addressable range of 8GBytes
Functional Safety:
- Functional Safety-Compliant targeted [Industrial]
- Developed for functional safety applications
- Documentation will be available to aid IEC 61508 functional safety system design
- Systematic capability up to SIL 3 targeted
- Hardware Integrity up to SIL 2 targeted
- Safety-related certification
- IEC 61508 by TÜV SÜD planned
- Functional Safety-Compliant targeted [Automotive]
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 functional safety system design
- Systematic capability up to ASIL D targeted
- Hardware integrity up to ASIL B targeted
- Safety-related certification
- ISO 26262 by TÜV SÜD planned
- AEC - Q100 qualified [Automotive]
Security:
- Secure boot supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-roll back protection
- Trusted Execution Environment (TEE) supported
- Arm TrustZone based TEE
- Extensive firewall support for isolation
- Secure watchdog/timer/IPC
- Secure storage support
- Replay Protected Memory Block (RPMB) support
- Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
- Cryptographic acceleration supported
- Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
- Supports cryptographic cores
- AES – 128-/192-/256-Bit key sizes
- SHA2 – 224-/256-/384-/512-Bit key sizes
- DRBG with true random number generator
- PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
- Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
- Debugging security
- Secure software controlled debug access
- Security aware debugging
High-Speed Interfaces:
- Integrated Ethernet switch supporting (total 2 external ports)
- RMII(10/100) or RGMII (10/100/1000)
- IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
- Clause 45 MDIO PHY management
- Packet Classifier based on ALE engine with 512 classifiers
- Priority based flow control
- Time Sensitive Networking (TSN) support
- Four CPU H/W interrupt Pacing
- IP/UDP/TCP checksum offload in hardware
- Two USB2.0 Ports
- Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
- Integrated USB VBUS detection
General Connectivity:
- 9x Universal Asynchronous Receiver-Transmitters (UART)
- 5x Serial Peripheral Interface (SPI) controllers
- 6x Inter-Integrated Circuit (I2C) ports
- 3x Multichannel Audio Serial Ports (McASP)
- Transmit and Receive Clocks up to 50MHz
- Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
- Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
- Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
- FIFO Buffers for Transmit and Receive (256 Bytes)
- Support for audio reference output clock
- 3x enhanced PWM modules (ePWM)
- 3x enhanced Quadrature Encoder Pulse modules (eQEP)
- 3x enhanced Capture modules (eCAP)
- General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
- 3x Controller Area Network (CAN) modules with CAN-FD support
- Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
- Full CAN FD support (up to 64 data bytes)
- Parity/ECC check for Message RAM
- Speed up to 8Mbps
Media and Data Storage:
- 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface
- 1x 8-bit eMMC interface up to HS200 speed
- 2x 4-bit SD/SDIO interface up to UHS-I
- Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
- 1× General-Purpose Memory Controller (GPMC) up to 133MHz
- Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH code to support 4-, 8-, or 16-bit ECC
- Uses Hamming code to support 1-bit ECC
- Error Locator Module (ELM)
- Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
- Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
- OSPI/QSPI with DDR / SDR support
- Support for Serial NAND and Serial NOR Flash devices
- 4GBytes memory address support
- XIP mode with optional on-the-fly encryption
Power Management:
- Low-power modes supported by Device/Power Manager
- Partial IO support for CAN/GPIO/UART wakeup
- DeepSleep : I/O + DDR (suspend to RAM)
- DeepSleep
- MCU Only
- Standby
- Dynamic frequency scaling for Cortex-A53
Boot Options:
- UART
- I2C EEPROM
- OSPI/QSPI Flash
- GPMC NOR/NAND Flash
- Serial NAND Flash
- SD Card
- eMMC
- USB (host) boot from Mass Storage device
- USB (device) boot from external host (DFU mode)
- Ethernet
Technology / Package:
- 16-nm FinFET technology
- 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCBGA (AMB)
- 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)
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