Texas Instruments AM6252BTCFHIALWRQ1
Manufacturer No:
AM6252BTCFHIALWRQ1
Manufacturer:
Texas Instruments
Package:
Description:
Automotive display SoC with embedded safety for digital clusters
Quantity:
In Stock :4094
Looking for price or availability? Send us an RFQ and our sales team will respond quickly.
Shipping & Availability
Fast worldwide shipping via DHL, FedEx, UPS, and EMS.
Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
Payment
We support multiple secure payment methods including PayPal, Visa, MasterCard, and American Express. All transactions are protected with advanced encryption to ensure secure and reliable payments.
Authenticity Guarantee
All components supplied by Aichiplink are sourced from trusted global suppliers and verified through strict in-house inspection and quality control procedures.
Quality Assurance
Certified in-house inspection and testing facilities ensure all components meet internationally recognized quality standards.
User Guide
Aichiplink operates certified in-house inspection and testing facilities to ensure all electronic components meet internationally recognized quality and compliance standards. Our quality management system is verified through ISO 9001 certification and industry-standard inspection procedures.
PURCHASE
Please verify all part numbers, quantities, and packaging preferences before placing your order. If substitutions are acceptable, please indicate this clearly. For time-sensitive projects, confirm estimated delivery dates and stock availability in advance. Once submitted, changes or cancellations may not be possible, especially for items marked as non-cancellable/non-returnable (NCNR). For international shipments, please ensure all import documentation is complete and accurate to avoid delays.
MEANS OF PAYMENTFor your convenience, we accept multiple payment methods in USD, including PayPal, Credit Card, and Wire Transfer. Net terms may be available for qualified customers upon approval.
RFQ (REQUEST FOR QUOTATIONS)Please ensure the part numbers and quantities are accurate and complete when submitting your RFQ.
Provide target prices and acceptable alternatives, if any, to speed up the quotation process.
Quotations are subject to stock availability and may vary with market conditions. Prices and lead times are not guaranteed until a purchase order is confirmed. Ensure your contact details are correct to avoid delays in response.
Step1：Prepare product
Step2：Desiccant Protection
Step3：Vacuum Packaging
Step4：Individual Package
Step5：Anti-collision Filling
Step6：Packaging Box
SHIPPING COST
1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.
Currently, our products are shipped through DHL, FedEx, SF, and UPS.
DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
AM6252BTCFHIALWRQ1 Information
Texas Instruments AM6252BTCFHIALWRQ1 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments AM6252BTCFHIALWRQ1.
- Type
- Parameter
- CPU
- 1 Arm Cortex-A53, 2 Arm Cortex-A53, 4 Arm Cortex-A53
- Frequency (MHz)
- 1400
- Coprocessors
- 1 Arm Cortex-M4F
- Graphics acceleration
- 1 3D
- Display type
- MIPI DPI, OLDI
- Protocols
- Ethernet, TSN
- Number of Ethernet ports
- 2
- Features
- Vision Analytics
- Operating system
- Android, Linux
- Security
- Secure boot
- Type
- Parameter
- TI functional safety category
- Functional Safety-Compliant
- Rating
- Automotive
- Power supply solution
- TPS65219
- Operating temperature range (°C)
- -40 to 125
- Package
- FCBGA (AMC)
- Pins
- 441
- Size
- 295.84 mm² 17.2 x 17.2
- Package
- FCCSP (ALW)
- Pins
- 425
- Size
- 169 mm² 13 x 13
Download datasheets and manufacturer documentation for Texas Instruments AM6252BTCFHIALWRQ1.
Data sheet:
User guide:
Application note:
Functional safety information:
Application brief:
The low-cost AM62x Sitara™ MPU family of application processors are built for Linux® application development. With scalable Arm® Cortex®-A53 performance and embedded features, such as dual-display support and 3D graphics acceleration, along with an extensive set of peripherals, making the AM62x device well-suited for a broad range of industrial and automotive applications while offering intelligent features and optimized power architecture.
Functional safety requirements can be addressed using the integrated Cortex-M4F cores and dedicated peripherals, which can all be isolated from the rest of the AM62x processor.
The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) capable. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM62x enable system-level connectivity, such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM62x device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications.
Products in the AM62x processor family:
- AM625 – Human-machine Interaction SoC with Arm® Cortex®-A53-based edge AI and full-HD dual-display
- AM625-Q1 – Automotive Display SoC with embedded safety for digital clusters
- AM623 – Internet of Things (IoT) and Gateway SoC with Arm® Cortex®-A53-based object and gesture recognition
- AM620-Q1 – Automotive Compute SoC with embedded safety for driver monitoring, networking and V2X systems
Processor Cores:
- Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
- Single-core Arm® Cortex®-M4F MCU at up to 400MHz
- 256KB SRAM with SECDED ECC
- Dedicated Device/Power Manager
Multimedia:
- Display subsystem
- Dual display support
- 1920x1080 @ 60fps for each display
- 1x 2048x1080 + 1x 1280x720
- Up to 165MHz pixel clock support with Independent PLL for each display
- OLDI (4 lanes LVDS - 2x) and DPI (24-bit RGB LVCMOS)
- Support safety feature such as freeze frame detection and MISR data check
- 3D Graphics Processing Unit
- 1 pixel per clock or higher
- Fillrate greater than 500Mpixels/sec
- >500MTexels/s, >8GFLOPs
- Supports at least 2 composition layers
- Supports up to 2048x1080 @60fps
- Supports ARGB32, RGB565 and YUV formats
- 2D graphics capable
- OpenGL ES 3.1, Vulkan 1.2
- One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
- MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
- Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane
- ECC verification/correction with CRC check + ECC on RAM
- Virtual Channel support (up to 16)
- Ability to write stream data directly to DDR via DMA
Memory Subsystem:
- Up to 816KB of On-chip RAM
- 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
- 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
- 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
- 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
- 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
- DDR Subsystem (DDRSS)
- Supports LPDDR4, DDR4 memory types
- 16-Bit data bus with inline ECC
- Supports speeds up to 1600MT/s
- Max addressable range
- 8GBytes with DDR4
- 4GBytes with LPDDR4
Functional Safety:
- Functional Safety-Compliant targeted [Automotive]
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 functional safety system design
- Systematic capability up to ASIL D targeted
- Hardware integrity up to ASIL B targeted
- Safety-related certification
- ISO 26262 by TUV SUD planned
- AEC - Q100 qualified
Security:
- Secure boot supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-roll back protection
- Trusted Execution Environment (TEE) supported
- Arm TrustZone based TEE
- Extensive firewall support for isolation
- Secure watchdog/timer/IPC
- Secure storage support
- Replay Protected Memory Block (RPMB) support
- Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
- Cryptographic acceleration supported
- Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
- Supports cryptographic cores
- AES – 128-/192-/256-Bit key sizes
- SHA2 – 224-/256-/384-/512-Bit key sizes
- DRBG with true random number generator
- PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
- Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
- Debugging security
- Secure software controlled debug access
- Security aware debugging
PRU Subsystem:
- Dual-core Programmable Real-Time Unit Subystem (PRUSS) running up to 333MHz
- Intended for driving GPIO for cycle accurate protocols such as additional:
- General Purpose Input/Output (GPIO)
- UARTs
- I2C
- External ADC
- 16KByte program memory per PRU with SECDED ECC
- 8KB data memory per PRU with SECDED ECC
- 32KB general purpose memory with SECDED ECC
- CRC32/16 HW accelerator
- Scratch PAD memory with 3 banks of 30 x 32-bit registers
- 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
- 1 interrupt controller (INTC), minimum of 64 input events supported
High-Speed Interfaces:
- Integrated Ethernet switch supporting (total 2 external ports)
- RMII(10/100) or RGMII (10/100/1000)
- IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
- Clause 45 MDIO PHY management
- Packet Classifier based on ALE engine with 512 classifiers
- Priority based flow control
- Time sensitive networking (TSN) support
- Four CPU H/W interrupt Pacing
- IP/UDP/TCP checksum offload in hardware
- Two USB2.0 Ports
- Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
- Integrated USB VBUS detection
General Connectivity:
- 9x Universal Asynchronous Receiver-Transmitters (UART)
- 5x Serial Peripheral Interface (SPI) controllers
- 6x Inter-Integrated Circuit (I2C) ports
- 3x Multichannel Audio Serial Ports (McASP)
- Transmit and Receive Clocks up to 50MHz
- Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
- Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
- Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
- FIFO Buffers for Transmit and Receive (256 Bytes)
- Support for audio reference output clock
- 3x enhanced PWM modules (ePWM)
- 3x enhanced Quadrature Encoder Pulse modules (eQEP)
- 3x enhanced Capture modules (eCAP)
- General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
- 3x Controller Area Network (CAN) modules with CAN-FD support
- Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
- Full CAN FD support (up to 64 data bytes)
- Parity/ECC check for Message RAM
- Speed up to 8Mbps
Media and Data Storage:
- 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface
- 1x 8-bit eMMC interface up to HS200 speed
- 2x 4-bit SD/SDIO interface up to UHS-I
- Compliant with eMMC 5.1, SD 3.0 and SDIO Version 3.0
- 1× General-Purpose Memory Controller (GPMC) up to 133MHz
- Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
- Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
- Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
- Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
- OSPI/QSPI with DDR / SDR support
- Support for Serial NAND and Serial NOR flash devices
- 4GBytes memory address support
- XIP mode with optional on-the-fly encryption
Power Management:
- Low power modes supported by Device/Power Manager
- Partial IO support for CAN/GPIO/UART wakeup
- DeepSleep
- MCU Only
- Standby
- Dynamic frequency scaling for Cortex-A53
Optimal Power Management Solution:
- Recommended TPS65219 Power Management ICs (PMIC)
- Companion PMIC specially designed to meet device power supply requirements
- Flexible mapping and factory programmed configurations to support different use cases
Boot Options:
- UART
- I2C EEPROM
- OSPI/QSPI Flash
- GPMC NOR/NAND Flash
- Serial NAND Flash
- SD Card
- eMMC
- USB (host) boot from Mass Storage device
- USB (device) boot from external host (DFU mode)
- Ethernet
Technology / Package:
- 16nm technology
- 13mm x 13mm, 0.5mm pitch, 425-pin FCCSP BGA (ALW)
- 17.2mm x 17.2mm, 0.8mm pitch, 441-pin FCBGA (AMC)
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
