Texas Instruments ADC3648IRTDT
Manufacturer No:
ADC3648IRTDT
Manufacturer:
Texas Instruments
Package:
Description:
14-bit two-channel 250MSPS ADC with LVDS interface and up to 32768x decimation
Quantity:
In Stock :2790
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Expected Shipping：Fri, May 29 - Sat, May 30, 2026
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Date Code：Within 2 Years
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ADC3648IRTDT Information
Texas Instruments ADC3648IRTDT technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments ADC3648IRTDT.
- Type
- Parameter
- Sample rate (max) (Msps)
- 250
- Resolution (Bits)
- 14
- Number of input channels
- 2
- Interface type
- DDR LVDS
- Analog input BW (MHz)
- 1400
- Features
- Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power
- Rating
- Catalog
- Peak-to-peak input voltage range (V)
- 2
- Power consumption (typ) (mW)
- 470
- Architecture
- Pipeline
- Type
- Parameter
- SNR (dB)
- 74
- ENOB (Bits)
- 12
- SFDR (dB)
- 83
- Operating temperature range (°C)
- -40 to 85
- Input buffer
- Yes
- Package
- VQFNP (RTD)
- Pins
- 64
- Size
- 81 mm² 9 x 9
- REACH Status
- Yes
- RoHS Status
- RoHS Compliant
Download datasheets and manufacturer documentation for Texas Instruments ADC3648IRTDT.
Data sheet:
Analog Design Journal:
The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).
The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).
The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.
The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.
- 14-bit, dual channel 250 and 500MSPS ADC
- Noise spectral density: -158.5dBFS/Hz
- Thermal Noise: 74.5dBFS
- Single core (non-interleaved) ADC architecture
- Power consumption:
- 300mW/channel (500MSPS)
- 250mW/channel (250MSPS)
- Aperture jitter: 75fs
- Buffered analog inputs
- Programmable 100Ω to 200Ω termination
- Input full scale: 2Vpp
- Full power input bandwidth (-3dB): 1.4GHz
- Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 73.8dBFS
- SFDR HD2,3: 84dBc
- SFDR worst spur: 90dBFS
- Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- DDR, Serial LVDS interface
- 14-bit Parallel DDR LVDS for DDC bypass
- 16-bit Serial LVDS for decimation
- 32-bit output option for high decimation
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12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
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