Texas Instruments ADC3569IRTDT
Manufacturer No:
ADC3569IRTDT
Manufacturer:
Texas Instruments
Package:
Description:
16-bit one-channel 500MSPS ADC with LVDS interface and up to 32768x decimation
Quantity:
In Stock :7209
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Date Code：Within 2 Years
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ADC3569IRTDT Information
Texas Instruments ADC3569IRTDT technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments ADC3569IRTDT.
- Type
- Parameter
- Sample rate (max) (Msps)
- 500
- Resolution (Bits)
- 16
- Number of input channels
- 1
- Interface type
- DDR LVDS
- Analog input BW (MHz)
- 1400
- Features
- Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power
- Rating
- Catalog
- Peak-to-peak input voltage range (V)
- 2
- Power consumption (typ) (mW)
- 413.1
- Architecture
- Pipeline
- Type
- Parameter
- SNR (dB)
- 75.2
- ENOB (Bits)
- 12.3
- SFDR (dB)
- 80
- Operating temperature range (°C)
- -40 to 105
- Input buffer
- Yes
- Package
- VQFNP (RTD)
- Pins
- 64
- Size
- 81 mm² 9 x 9
- REACH Status
- Yes
- RoHS Status
- RoHS Compliant
Download datasheets and manufacturer documentation for Texas Instruments ADC3569IRTDT.
Data sheet:
Analog Design Journal:
The ADC3568 and ADC3569 (ADC356x) are 16-bit, 250MSPS and 500MSPS, single channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -160dBFS/Hz (500MSPS).
The power efficient ADC architecture consumes 435mW at 500MSPS and provides power scaling with lower sampling rates (369mW at 250MSPS).
The ADC356x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.
The ADC356x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a parallel SDR or DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.
- 16-bit, single channel 250 and 500MSPS ADC
- Noise spectral density: −160.4dBFS/Hz
- Thermal Noise: 76.4dBFS
- Single core (non-interleaved) ADC architecture
- Power consumption:
- 435mW (500MSPS)
- 369mW (250MSPS)
- Aperture jitter: 75fs
- Buffered analog inputs
- Programmable 100Ω and 200Ω termination
- Input fullscale: 2VPP
- Full power input bandwidth (−3dB): 1.4GHz
- Spectral performance (fIN = 70MHz, −1dBFS):
- SNR: 75.6dBFS
- SFDR HD2,3: 80dBc
- SFDR worst spur: 94dBFS
- INL: ±2 LSB (typical)
- DNL: ±0.5 LSB (typical)
- Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- Parallel/ Serial LVDS interface
- 16-bit Parallel SDR, DDR LVDS for DDC bypass
- Serial LVDS for decimation
- 32-bit output option for high decimation
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12.28 M
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3,000+
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