Texas Instruments ADC12DL500ACF
Manufacturer No:
ADC12DL500ACF
Manufacturer:
Texas Instruments
Package:
Description:
12-bit, dual 500MSPS or single 1GSPS analog-to-digital converter (LVDS interface)
Quantity:
In Stock :5883
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Expected Shipping：Fri, May 29 - Sat, May 30, 2026
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Date Code：Within 2 Years
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ADC12DL500ACF Information
Texas Instruments ADC12DL500ACF technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments ADC12DL500ACF.
- Type
- Parameter
- Sample rate (max) (Msps)
- 500, 1000
- Resolution (Bits)
- 12
- Number of input channels
- 1, 2
- Interface type
- DDR LVDS, Parallel LVDS
- Analog input BW (MHz)
- 8000
- Features
- Ultra High Speed
- Rating
- Catalog
- Peak-to-peak input voltage range (V)
- 0.8
- Power consumption (typ) (mW)
- 2500
- Architecture
- Folding Interpolating
- Type
- Parameter
- SNR (dB)
- 56.8
- ENOB (Bits)
- 9
- SFDR (dB)
- 69
- Operating temperature range (°C)
- -40 to 85
- Input buffer
- Yes
- Package
- FCBGA (ACF)
- Pins
- 256
- Size
- 289 mm² 17 x 17
- REACH Status
- Yes
- RoHS Status
- RoHS Compliant
Download datasheets and manufacturer documentation for Texas Instruments ADC12DL500ACF.
Data sheet:
Technical article:
The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications.
The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.
- ADC core:
- 12-Bit resolution
- Up to 1GSPS, 3GSPS, 5GSPS in single-channel mode
- Up to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel mode
- Internal dither for low-magnitude, high-order harmonics
- Low-latency LVDS interface:
- Total latency: < 10ns
- Up to 48 data pairs at 1.6Gbps
- Four DDR data clocks
- Strobe signals simplify synchronization
- Noise floor (no input, VFS = 1VPP-DIFF):
- Dual-channel mode: -143.5, -148, -149.8dBFS/Hz
- Single-channel mode: -146.2, -150.3, -152.2dBFS/Hz
- Buffered analog inputs with VCMI of 0V:
- Analog input bandwidth (–3dB): 8GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (TAD) adjustment:
- Precise sampling control: 19fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- Power consumption: 2.6, 2.8, 3W
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