Renesas 9DBL0641BKILFT
Manufacturer No:
9DBL0641BKILFT
Manufacturer:
Renesas
Package:
Description:
6-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
Quantity:
In Stock :7622
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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PURCHASE
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SHIPPING COST
1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.
Currently, our products are shipped through DHL, FedEx, SF, and UPS.
DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
9DBL0641BKILFT Information
Renesas 9DBL0641BKILFT technical specifications, attributes, parameters and parts with similar specifications to Renesas 9DBL0641BKILFT.
- Type
- Parameter
- Lead Count (#)
- 40
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 2500
- Qty. per Carrier (#)
- 0
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- -40 to +85°C
- Accepts Spread Spec Input
- Yes
- Additive Phase Jitter Typ RMS (fs)
- 300
- Type
- Parameter
- Additive Phase Jitter Typ RMS (ps)
- 0.3
- Advanced Features
- Multiple SMBus addresses
- App Jitter Compliance
- PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5
- Architecture
- Common, SRNS, SRIS
- C-C Jitter Max P-P (ps)
- 50
- Core Voltage (V)
- 3.3
- Diff. Input Signaling
- HCSL
- Diff. Inputs
- 1
- Diff. Output Signaling
- LP-HCSL
- Diff. Outputs
- 6
Download datasheets and manufacturer documentation for Renesas 9DBL0641BKILFT.
Datasheet:
The 9DBL0641 6-output zero-delay/fanout buffer is a 3.3V member of Renesas' full-featured PCIe family. The 9DBL0641 supports PCIe Gen 1 through Gen 5 and both Common and Independent Reference Clock architectures.
- Additive PCIe Gen 5 CC jitter < 60fs RMS (fanout mode)
- PCIe Gen 5 CC jitter < 150fs RMS (High-BW Zero Delay Buffer (ZDB) mode)
- 6 low-power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
- Direct connection to 100Ω transmission lines
- Dedicated OE# pin for each output
- Spread spectrum tolerant
- Pin or SMBus configuration
- 3 selectable SMBus addresses
- SMBus interface not required for device operation
- Easy AC coupling to other logic families, see application note AN-891
- Space-saving 40-pin 5mm × 5mm VFQFPN
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
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