Renesas 9DB801CFLFT
Manufacturer No:
9DB801CFLFT
Manufacturer:
Renesas
Package:
Description:
8-output Differential Buffer for PCIe Gen1
Quantity:
In Stock :8413
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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9DB801CFLFT Information
Renesas 9DB801CFLFT technical specifications, attributes, parameters and parts with similar specifications to Renesas 9DB801CFLFT.
- Type
- Parameter
- Lead Count (#)
- 48
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 1
- Qty. per Reel (#)
- 1000
- Qty. per Carrier (#)
- 0
- Chipset Name
- DB800
- Input Freq (MHz)
- 0 - 200
- Package Area (mm²)
- 119.3
- Pitch (mm)
- 0.64
- Pkg. Dimensions (mm)
- 15.9 x 7.5 x 2.3
- Type
- Parameter
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- 0 to 70°C
- Accepts Spread Spec Input
- Yes
- Advanced Features
- HW PLL mode control
- App Jitter Compliance
- PCIe Gen1
- Architecture
- Common
- C-C Jitter Max P-P (ps)
- 50
- Core Voltage (V)
- 3.3
- Diff. Input Signaling
- HCSL
Download datasheets and manufacturer documentation for Renesas 9DB801CFLFT.
The 9DB801C is a DB800 Version 2.0 Yellow Cover part with PCI Express® support. It can be used in PC or embedded systems to provide outputs that have low cycle-to-cycle jitter (50 ps), low output-to-output skew (100 ps), and are PCI Express® gen 1 compliant. The 9DB801C supports a 1 to 8 output configuration, taking a spread or non spread differential HCSL input from a CK410(B) main clock such as 954101 and 932S401, or any other differential HCSL pair. 9DB801C can generate HCSL or LVDS outputs from 50 to 200 MHz in PLL mode or 0 to 400 MHz in bypass mode. There are two de-jittering modes available selectable through the HIGH_BW# input pin, high bandwidth mode provides de-jittering for spread inputs and low bandwidth mode provides extra de-jittering for non-spread inputs. The SRC_STOP#, PD#, and individual OE# real-time input pins provide completely programmable power management control.
- 8 - 0.7 V current-mode differential output pairs
- Supports zero delay buffer mode and fanout mode
- Bandwidth programming available
- Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread.
- Supports undriven differential outputs in PD# and SRC_STOP# modes for power management.
- Supports polarity inversion to the output enables, SRC_STOP and PD.
- Outputs cycle-cycle jitter < 50 ps
- Outputs skew: 50 ps
- 50 - 200 MHz operation
- Extended frequency range in bypass mode to 400 MHz
- PCI Express® Gen I compliant
- Real time PLL lock detect output pin
- 48-pin SSOP/TSSOP package
- Available in RoHS compliant packaging
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12.28 M
Listed Part Number
3,000+
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4.9 M
In-stock SKU
15,000+
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