Renesas 8V19N492NLGI8
Manufacturer No:
8V19N492NLGI8
Manufacturer:
Renesas
Package:
Description:
3.135V~3.465V 2.949GHz Three-Wire Interface 5 VFQFPN-88(10x10) Clock Generators, PLLs, Frequency Synthesizers ROHS
Quantity:
In Stock :9677
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Shipped from：HK Warehouse
Expected Shipping：Tue, Jun 2 - Wed, Jun 3, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
8V19N492NLGI8 Information
Renesas 8V19N492NLGI8 technical specifications, attributes, parameters and parts with similar specifications to Renesas 8V19N492NLGI8.
- Type
- Parameter
- Lead Count (#)
- 88
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 2500
- Qty. per Carrier (#)
- 0
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- -40 to +85°C
- Country of Assembly
- Taiwan
- Country of Wafer Fabrication
- Singapore, United States
- Type
- Parameter
- Accepts Spread Spec Input
- No
- Additive Phase Jitter Typ RMS (fs)
- 63.1
- Additive Phase Jitter Typ RMS (ps)
- 0.063
- Adjustable Phase
- Yes
- Advanced Features
- Holdover, Phase Delay, Input Switching, JESD204B, Programmable Clock
- Channels (#)
- 1
- Core Voltage (V)
- 3.3
- DPLL Channels (#)
- 0
- Feedback Divider Resolution (bits)
- 12
- Fractional Output Dividers (#)
- 0
Download datasheets and manufacturer documentation for Renesas 8V19N492NLGI8.
Datasheet:
The 8V19N492 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks.
- High-performance clock RF-PLL with support for JESD204B
- Optimized for low phase noise: -150dBc/Hz (800kHz offset; 245.76MHz clock)
- Integrated phase noise of 63fs RMS typical (12k–20MHz).
- Dual-PLL architecture
- 1st-PLL stage with external VCXO for clock jitter attenuation
- 2nd-PLL with internal FemtoClock NG PLL: 2949.12MHz
- For 3932.16MHz: see 8V19N492-39
- For 3686.4MHz: see 8V19N491-36
- For 2457.6MHz: see 8V19N490-24 and 8V19N491-24
- For 1966.08MHz: see 8V19N490-19
- Five output channels with a total of 15 outputs
- Configurable integer clock frequency dividers
- Supported clock output frequencies include: 2949.12, 1474.56, 983.04, 491.52, 245.76, and 122.88 MHz
- Low-power LVPECL/LVDS outputs support configurable signal amplitude
- Phase delay circuits
- Redundant input clock architecture with two inputs and
- SYSREF generation modes include internal and external trigger mode for JESD204B
- Supply voltage: 3.3V
- Package: 10 × 10 mm, 88-VFQFPN
- Temperature range: -40°C to +105°C (Case)
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
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