Renesas 8V19N491-36BDGI
Manufacturer No:
8V19N491-36BDGI
Manufacturer:
Renesas
Package:
Description:
JESD204B/C Clock Jitter Attenuator
Quantity:
In Stock :2710
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
8V19N491-36BDGI Information
Renesas 8V19N491-36BDGI technical specifications, attributes, parameters and parts with similar specifications to Renesas 8V19N491-36BDGI.
- Type
- Parameter
- Lead Count (#)
- 100
- Carrier Type
- Tray
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 0
- Qty. per Carrier (#)
- 168
- Pb (Lead) Free
- Yes
- Pb Free Category
- e1 SnAgCu
- Temp. Range
- -40 to +85°C
- Accepts Spread Spec Input
- No
- Adjustable Phase
- Yes
- Type
- Parameter
- Advanced Features
- Holdover, Phase Delay, Input Switching, JESD204B, Programmable Clock
- Channels (#)
- 1
- Core Voltage (V)
- 3.3
- DPLL Channels (#)
- 0
- Feedback Divider Resolution (bits)
- 12
- Fractional Output Dividers (#)
- 0
- Frequency Plan
- 3686.4 / Output_Divider
- Input Freq (MHz)
- 30.72 - 2000
- Input Redundancy
- Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock
- Input Ref. Divider Resolution (bits)
- 12
Download datasheets and manufacturer documentation for Renesas 8V19N491-36BDGI.
The 8V19N491-36 is a fully integrated FemtoClock™ NG jitter attenuator and clock synthesizer. The device is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.
- High-performance clock RF-PLL with support for JESD204B
- Optimized for low phase noise: -152.5dBc/Hz (800kHz offset; 245.76MHz clock)
- Integrated phase noise of 65fs RMS typical (12kHz to 20MHz) at 737.28MHz
- Dual-PLL architecture
- First PLL stage with external VCXO for clock jitter attenuation
- Second PLL with internal FemtoClock NG PLL: 3686.4MHz
- For 3932.16MHz: see 8V19N492-39
- For 2949.12MHz: see 8V19N492 and 8V19N490A
- For 2457.6MHz: see 8V19N490-24 and 8V19N491-24
- For 1966.08MHz: see 8V19N490-19
- Five output channels with a total of 18 outputs
- Configurable integer clock frequency dividers
- Supported clock output frequencies include: 3686.4, 1843.2, 1228.8, 737.28, 614.4, 368.4, 307.2, 245.76, 153.6, 122.88, and 61.44 MHz
- Low-power LVPECL/LVDS outputs support configurable signal amplitude
- Phase delay circuits
- Redundant input clock architecture with four inputs including input activity monitoring and switching
- SYSREF generation modes include internal and external trigger mode for JESD204B
- Supply voltage: 3.3V
- SPI Interface, 3/4 wire configurable
- Package: 11mm x 11mm, 100-CABGA
- Temperature range: -40 °C to +85 °C
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
