Renesas 8V19N472BFGI
Manufacturer No:
8V19N472BFGI
Manufacturer:
Renesas
Package:
Description:
Clock Jitter Attenuator
Quantity:
In Stock :5037
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
8V19N472BFGI Information
Renesas 8V19N472BFGI technical specifications, attributes, parameters and parts with similar specifications to Renesas 8V19N472BFGI.
- Type
- Parameter
- Lead Count (#)
- 81
- Carrier Type
- Tray
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 0
- Qty. per Carrier (#)
- 360
- Pb (Lead) Free
- Yes
- Pb Free Category
- e1 SnAgCu
- Temp. Range
- -40 to +85°C
- Adjustable Phase
- Yes
- Advanced Features
- Holdover, Phase Delay, Input Switching, Programmable Clock
- Type
- Parameter
- Channels (#)
- 1
- Core Voltage (V)
- 3.3
- DPLL Channels (#)
- 0
- Feedback Divider Resolution (bits)
- 15
- Fractional Output Dividers (#)
- 1
- Frequency Plan
- 2949.12 / Output_Divider, 2457.6 / Output_Divider, 2500 / Output_Divider
- Input Freq (MHz)
- 0.008 - 307.2
- Input Redundancy
- Input Monitor, Auto-switch, Manual switch, Revertive and non-revertive switch, Holdover
- Input Ref. Divider Resolution (bits)
- 15
- Input Type
- LVDS, LVPECL
Download datasheets and manufacturer documentation for Renesas 8V19N472BFGI.
The 8V19N472 is a fully integrated FemtoClock NG Jitter Attenuator and Clock Synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations.
- High-performance clock RF-PLL
- Optimized for low phase noise: < -150dBc/Hz (1MHz offset; 245.76MHz clock)
- Dual-PLL architecture
- 1st-PLL stage with external VCXO for clock jitter attenuation
- 2nd-PLL stage with internal FemtoClock NG PLL at selectable 2949.12MHz and MHz (2400–2500MHz) VCO frequency
- Six output banks with a total of 12 outputs
- Supported clock output frequencies include:
- From VCO-0: 2949.12, 1474.56, 983.04, 491.52, 368.64, 122.88MHz
- From VCO-1: 2457.6, 1228.8, 614.4, 307.2, 153.6, 76.8MHz
- From the fractional output divider: 80–300MHz
- Clock channels with integer output divider contain a phase delay circuit with 512 steps of half of the selected VCO period
- Low-power LVPECL/LVDS outputs support configurable signal amplitude, DC and AC coupling and LVPECL, LVDS line terminations techniques
- Redundant input clock architecture
- Two inputs with an individual input signal monitor
- Digital holdover
- Manual and automatic clock selection
- Hitless switching
- Package: 81-FPBGA (8 × 8 mm, 0.8mm ball pitch)
- Temperature range: -40°C to +85°C
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
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