Renesas 8T39S11ANLGI8
Manufacturer No:
8T39S11ANLGI8
Manufacturer:
Renesas
Package:
Description:
IC CLK BUFFER 3:11 2GHZ.Clock Fanout Buffer (Distribution), Multiplexer IC 3:11 2 GHz
Quantity:
In Stock :7068
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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8T39S11ANLGI8 Information
Renesas 8T39S11ANLGI8 technical specifications, attributes, parameters and parts with similar specifications to Renesas 8T39S11ANLGI8.
- Type
- Parameter
- Lead Count (#)
- 48
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 2000
- Qty. per Carrier (#)
- 0
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- -40 to 85°C
- Additive Phase Jitter Typ RMS (fs)
- 26
- Additive Phase Jitter Typ RMS (ps)
- 0.026
- Type
- Parameter
- Core Voltage (V)
- 3.3, 2.5
- Family Name
- 8T39S
- Function
- Buffer, Multiplexer
- Input Freq (MHz)
- 0 - 250
- Input Type
- Crystal, HCSL, LVDS, LVPECL
- Inputs (#)
- 3
- Length (mm)
- 7.0
- MOQ
- 2000
- Output Banks (#)
- 2
- Output Freq Range (MHz)
- 0 - 250
Download datasheets and manufacturer documentation for Renesas 8T39S11ANLGI8.
Datasheets:
The 8T39S11A is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock. The selected signal is distributed to ten differential outputs which can be configured as LVPECL, LVDS, or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.
- Two differential reference clock input pairs
- Differential input pairs can accept the following differential input levels: LVPECL, LVDS, HCSL, HSTL, or single-ended
- Crystal input accepts 10MHz to 40MHz crystal or single-ended clock
- Maximum output frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz - Two banks, each has five differential output pairs that can be configured as LVPECL, LVDS, or HCSL
- One single-ended reference output with synchronous enable to avoid clock glitch
- Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level) - Part-to-part skew: 200ps (typical)
- Additive RMS phase jitter at 156.25MHz:
5.6fs RMS (10kHz to 1MHz), typical at 3.3V/3.3V
34.7fs RMS (12kHz to 20MHz), typical at 3.3V/3.3V - Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V - -40 °C to 85 °C ambient operating temperature
- Lead-free (RoHS 6) packaging
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12.28 M
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