Renesas 8725BM-21LF
Manufacturer No:
8725BM-21LF
Manufacturer:
Renesas
Package:
Description:
Differential to HSTL Zero Delay Buffer Clock Generator
Quantity:
In Stock :9990
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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8725BM-21LF Information
Renesas 8725BM-21LF technical specifications, attributes, parameters and parts with similar specifications to Renesas 8725BM-21LF.
- Type
- Parameter
- Lead Count (#)
- 20
- Carrier Type
- Tube
- Moisture Sensitivity Level (MSL)
- 1
- Qty. per Reel (#)
- 0
- Qty. per Carrier (#)
- 37
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- 0 to 70°C
- C-C Jitter Max P-P (ps)
- 50
- Core Voltage (V)
- 3.3
- Type
- Parameter
- Divider Value
- 1, 2, 4, 8
- Feedback Divider
- 1 - 1, 2 - 2, 4 - 4, 8 - 8
- Input Freq (MHz)
- 31.25 - 630
- Input Type
- LVPECL, LVDS, HSTL, HCSL, SSTL
- Inputs (#)
- 1
- Length (mm)
- 12.8
- MOQ
- 37
- Output Banks (#)
- 1
- Output Freq Range (MHz)
- 31.25 - 630
- Output Signaling
- HSTL
Download datasheets and manufacturer documentation for Renesas 8725BM-21LF.
The 8725B-21 is a highly versatile 1:1 differential-to-HSTL clock generator. The CLK, nCLK pair can accept most standard differential input levels. The 8725B-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier, or divider, and has an output frequency range of 31.25MHz to 630MHz. The reference divider, feedback divider, and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
- One differential HSTL output pair
One differential feedback output pair - Differential CLK, nCLK input pair
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, and SSTL
- Output frequency range: 31.25MHz to 630MHz
- Input frequency range: 31.25MHz to 630MHz
- VCO range: 250MHz to 630MHz
- External feedback for “zero delay” clock regeneration with configurable frequencies
- Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
- Cycle-to-Cycle jitter: 50ps (maximum)
- Output skew: 50ps (maximum)
- Static phase offset: 200ps (maximum)
- 3.3V core, 1.8V output operating supply
- 0 °C to 70 °C ambient operating temperature
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
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