82V3352TF-Renesas-Price, Stock & Datasheet

The 82V3352 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. The T0 path supports three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a serial microprocessor interface. The device supports Serial microprocessor interface mode only.

Features 0.1 Hz to 560 Hz bandwidth
Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet
Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements
Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, SMC, 4E and 4 clocks
Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components
Supports Forced or Automatic operating mode switch controlled by an internal state machine
the primary operating modes are Free- Run, Locked and Holdover
Supports programmable DPLL bandwidth (0.1 Hz to 560 Hz in 11 steps) and damping factor (1.2 to 20 in 5 steps)
Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy
Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds
Supports programmable input-to-output phase offset adjustment
Limits the phase and frequency offset of the outputs
Supports manual and automatic selected input clock switch
Supports automatic hitless selected input clock switch on clock failure
Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing
Provides three 2 kHz, 4 kHz or 8 kHz frame sync input signals, and a 2 kHz and an 8 kHz frame sync output signals
Provides 5 input clocks whose frequency cover from 2 kHz to 622.08 MHz
Provides 2 output clocks whose frequency cover from 1 Hz to 622.08 MHz
Provides output clocks for BITS, GPS, 3G, GSM, etc.
Supports PECL/LVDS and CMOS input/output technologies
Supports master clock calibration
Supports Line Card application
Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria
Serial microprocessor interface mode
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation with 5 V tolerant CMOS I/Os
64-pin TQFP package, Green package options available

Renesas 82V3352TF

Manufacturer No:

82V3352TF

Manufacturer:

Renesas

Package:

Description:

Synchronous Ethernet WAN PLL

In Stock :9953

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82V3352TF Information

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82V3352TF Relevant information

5P49V5901B025NLGI8

R7F100GGH2DFB#HA0

XLP538660.000000X

UPC811G2-E1-AP

74ALVCH16240PV8

IDT74FCT646HTP

8N3DV85EC-0110CDI8

6V40143PGG8

R5F565NCDDLJ#20

UPC842G2(74)-A