82V32021NLG8-Renesas-Price, Stock & Datasheet

The 82V32021 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. An input clock is automatically or manually selected for DPLL locking. The DPLL supports three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0 APLL, the outputs of the device will be in a better jitter/wander performance. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed only through an I2C programming interface.

Features 1.2 Hz to 560 Hz bandwidth
Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements
Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including 4E and 4 clocks
Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components
Supports Forced or Automatic operating mode switch controlled by an internal state machine
the primary operating modes are Free- Run, Locked and Holdover
Supports programmable DPLL bandwidth (1.2 Hz to 560 Hz in 8 steps) and damping factor (1.2 to 20 in 5 steps)
Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy
Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds
Limits the phase and frequency offset of the output
Supports manual and automatic selected input clock switch
Supports automatic hitless selected input clock switch on clock failure
Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing
Provides two 2 kHz, 4 kHz or 8 kHz frame sync input signals, and an 8 kHz frame sync output signal
Provides two input clocks whose frequency cover from 2 kHz to 155.52 MHz
Provides one output clock whose frequency covers from 1Hz to 155.52 MHz
Provides output clocks for BITS, GPS, 3G, GSM, etc.
Supports CMOS input/output
Supports master clock calibration
Supports Line Card application
Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria
I2C programming interface
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation with 5 V tolerant CMOS I/Os
68-pin VFQFPN package, Green package options available

Renesas 82V32021NLG8

Manufacturer No:

82V32021NLG8

Manufacturer:

Renesas

Package:

Description:

EBU WAN PLL

In Stock :9260

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