Renesas 82V3155PV
Manufacturer No:
82V3155PV
Manufacturer:
Renesas
Package:
Description:
Enhanced T1/E1/OC3 WAN PLL With Dual Reference Inputs
Quantity:
In Stock :3930
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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82V3155PV Information
Renesas 82V3155PV technical specifications, attributes, parameters and parts with similar specifications to Renesas 82V3155PV.
- Type
- Parameter
- Pkg. Type
- SSOP
- Lead Count (#)
- 56
- Pb (Lead) Free
- No
- Carrier Type
- Tube
- App Jitter Compliance
- TR62411, GR-1244-CORE, ETS 300 011, ITU-T G.813 (Option 1), ITU-T G.812
- Core Voltage (V)
- 3.3
- Input Freq (MHz)
- 0.008 - 0.008, 1.544 - 1.544, 2.048 - 2.048, 19.44 - 19.44
- Input Type
- LVCMOS
- Inputs (#)
- 2
- Length (mm)
- 18.4
- Type
- Parameter
- MOQ
- 26
- Moisture Sensitivity Level (MSL)
- 1
- Output Banks (#)
- 17
- Output Freq Range (MHz)
- 0.008 - 0.008, 1.544 - 1.544, 3.088 - 3.088, 6.312 - 6.312, 2.048 - 2.048, 4.096 - 4.096, 8.192 - 8.192, 16.384 - 16.384, 19.44 - 19.44, 32.768 - 32.768, 155.52 - 155.52
- Output Type
- LVCMOS, LVDS
- Output Voltage (V)
- 3.3
- Outputs (#)
- 17
- Package Area (mm²)
- 138.0
- Pb Free Category
- e0
- Pitch (mm)
- 0.64
Download datasheets and manufacturer documentation for Renesas 82V3155PV.
The 82V3155 is an enhanced T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS, 19.44 MHz and 155.52 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3155 provides 10 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o, C155) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3155 is compliant with AT&T TR62411, Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced, Stratum 4, OC-3 port, 155.52 Mbit/s application and ETSI ETS 300 011, ITU-T G.813 Option 1, and ITU-T G.812 Type IV clocks. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE (Maximum Time Interval Error) requirements for these specifications. The 82V3155 can be used in synchronization and timing control for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse source. It also can be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs (Integrated Access Devices), PBXs, line cards and SONET/SDH equipments.
- Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application
- Supports ITU-T G.813 Option 1 clocks
- Supports ITU-T G.812 Type IV clocks
- Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface
- Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz
- Accepts two independent reference inputs which may have same or different nominal frequencies applied to them
- Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o, C32o and C155 output clock signals
- Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,F32o, RSP and TSP
- Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1
- Holdover frequency accuracy of 0.025 ppm
- Phase slope of 5 ns per 125 ?s
- Attenuates wander from 2.1 Hz
- Fast lock mode
- Provides Time Interval Error (TIE) correction
- MTIE of 600 ns
- JTAG boundary scan
- Holdover status indication
- Freerun status indication
- Normal status indication
- Lock status indication
- Input reference quality indication
- 3.3 V operation with 5 V tolerant I/O
- Package available: 56-pin SSOP (Green option available)
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
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