Renesas 71V3558S200PFG8
Manufacturer No:
71V3558S200PFG8
Manufacturer:
Renesas
Package:
Description:
3.3V 256K x 18 ZBT Synchronous Pipelined SRAM with 3.3V I/O
Quantity:
In Stock :5173
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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SHIPPING COST
1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
71V3558S200PFG8 Information
Renesas 71V3558S200PFG8 technical specifications, attributes, parameters and parts with similar specifications to Renesas 71V3558S200PFG8.
- Type
- Parameter
- Lead Count (#)
- 100
- Pb (Lead) Free
- Yes
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 3
- Architecture
- ZBT
- Bus Width (bits)
- 18
- Core Voltage (V)
- 3.3
- Density (Kb)
- 4608
- I/O Frequency (MHz)
- 1 - 1
- I/O Voltage (V)
- 2.5 - 2.5
- Type
- Parameter
- Length (mm)
- 20.0
- MOQ
- 1000
- Organization
- 256K x 18
- Output Type
- Pipelined
- Package Area (mm²)
- 280.0
- Pb Free Category
- e3 Sn
- Pitch (mm)
- 0.65
- Pkg. Dimensions (mm)
- 20.0 x 14.0 x 1.4
- Pkg. Type
- TQFP
- Qty. per Carrier (#)
- 0
Download datasheets and manufacturer documentation for Renesas 71V3558S200PFG8.
The 71V3558 3.3V CMOS synchronous SRAM, organized as 256K x 18, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V3558 contains data I/O, address, and control signal registers.
- Supports high-performance system speed - 200MHz (x18) (3.2ns Clock-to-Data access)
- ZBT feature - No dead cycles between write and read cycles
- Internally synchronized output buffer enable eliminates the need to control OE
- Single R/W (Read/Write) control pin
- Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
- 4-word burst capability (interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- 3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
- Optional- Boundary Scan JTAG interface (IEEE 1149.1 compliant)
- Available in 100-pin TQFP and 165 fpBGA packages
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
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