Renesas 70V657S10BF8
Manufacturer No:
70V657S10BF8
Manufacturer:
Renesas
Package:
Description:
32K x 36 3.3V Dual-Port RAM, Interleaved I/O's
Quantity:
In Stock :9093
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
70V657S10BF8 Information
Renesas 70V657S10BF8 technical specifications, attributes, parameters and parts with similar specifications to Renesas 70V657S10BF8.
- Type
- Parameter
- Lead Count (#)
- 208
- Pb (Lead) Free
- No
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 3
- Access Time (ns)
- 10
- Architecture
- Dual-Port
- Bus Width (bits)
- 36
- Core Voltage (V)
- 3.3
- Density (Kb)
- 1152
- Function
- Interrupt
- Type
- Parameter
- I/O Type
- 3.3 V LVTTL
- Interface
- Async
- Length (mm)
- 15
- MOQ
- 1000
- Organization
- 32K x 36
- Package Area (mm²)
- 225.0
- Pb Free Category
- e0
- Pitch (mm)
- 0.8
- Pkg. Dimensions (mm)
- 15.0 x 15.0 x 1.4
- Pkg. Type
- CABGA
Download datasheets and manufacturer documentation for Renesas 70V657S10BF8.
The 70V657 is a high-speed 32K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.
- Dual-Port allows simultaneous access of the same memory location
- Dual chip enables allow for depth expansion without external logic
- Easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device
- Busy and Interrupt Flags
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port
- Separate byte controls for multiplexed bus and bus matching compatibility
- Includes JTAG functionality on BGA package versions only
- LVTTL-compatible, single 3.3V (±150mV) power supply for core
- LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
- Available in a 208-pin PQFP, 208-ball fpBGA and 256-ball BGA
- Industrial temperature range (–40C to +85C) is available
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
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