Renesas 70V639S15BC
Manufacturer No:
70V639S15BC
Manufacturer:
Renesas
Package:
Description:
128K x 18 3.3V Dual-Port RAM, Interleaved I/Os
Quantity:
In Stock :7188
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
70V639S15BC Information
Renesas 70V639S15BC technical specifications, attributes, parameters and parts with similar specifications to Renesas 70V639S15BC.
- Type
- Parameter
- Lead Count (#)
- 256
- Pb (Lead) Free
- No
- Carrier Type
- Tray
- Moisture Sensitivity Level (MSL)
- 4
- Access Time (ns)
- 15
- Architecture
- Dual-Port
- Bus Width (bits)
- 18
- Core Voltage (V)
- 3.3
- Density (Kb)
- 2304
- Function
- Busy, Interrupt, JTAG, Master, Slave
- Type
- Parameter
- I/O Type
- 3.3 V LVTTL
- Interface
- Async
- Length (mm)
- 17
- MOQ
- 24
- Organization
- 128K x 18
- Package Area (mm²)
- 289.0
- Pb Free Category
- e0
- Pitch (mm)
- 1
- Pkg. Dimensions (mm)
- 17.0 x 17.0 x 1.4
- Pkg. Type
- CABGA
Download datasheets and manufacturer documentation for Renesas 70V639S15BC.
The 70V639 is a high-speed 128K x 18 asynchronous dual-port static RAM designed to be used as a stand-alone dual-port RAM or as a combination Master/Slave dual-port RAM for 36-bit or more word systems. Using the Master/Slave dual-port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power-down feature controlled by the chip enables (either CE0 or CE1) permits the on-chip circuitry of each port to enter a very low standby power mode.
- Dual-port allows simultaneous access of the same memory location
- Dual chip enables allow for depth expansion without external logic
- Easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device
- Busy and Interrupt flags
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports; fully asynchronous operation from either port
- Separate byte controls for multiplexed bus and bus-matching compatibility
- Includes JTAG functionality on BGA package versions only
- LVTTL-compatible, single 3.3V (±150mV) power supply for core
- LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
- Available in a 128-pin TQFP, 208-ball fpBGA, and 256-ball BGA
- Industrial temperature range (–40 °C to +85 °C) is available
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12.28 M
Listed Part Number
3,000+
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In-stock SKU
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