Renesas 70T659S12BF
Manufacturer No:
70T659S12BF
Manufacturer:
Renesas
Package:
Description:
128K x 36 Async, 3.3V/2.5V Dual-Port RAM, Interleaved I/Os
Quantity:
In Stock :3111
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
70T659S12BF Information
Renesas 70T659S12BF technical specifications, attributes, parameters and parts with similar specifications to Renesas 70T659S12BF.
- Type
- Parameter
- Carrier Type
- Tray
- Moisture Sensitivity Level (MSL)
- 4
- Access Time (ns)
- 12
- Architecture
- Dual-Port
- Bus Width (bits)
- 36
- Core Voltage (V)
- 2.5
- Density (Kb)
- 4608
- Function
- Busy, Interrupt, JTAG, Master, Semaphore, Slave, Sleep Mode
- I/O Type
- 2.5 V LVTTL, 3.3 V LVTTL
- Interface
- Async
- Type
- Parameter
- Lead Count (#)
- 208
- Length (mm)
- 15
- MOQ
- 21
- Organization
- 128K x 36
- Package Area (mm²)
- 225.0
- Pb (Lead) Free
- No
- Pb Free Category
- e0
- Pitch (mm)
- 0.8
- Pkg. Dimensions (mm)
- 15.0 x 15.0 x 1.4
- Pkg. Type
- CABGA
Download datasheets and manufacturer documentation for Renesas 70T659S12BF.
The 70T659 is a high-speed 128K x 36 asynchronous dual-port static RAM designed to be used as a stand-alone dual-port RAM or as a combination Master/Slave dual-port RAM for 72-bit or more word systems, which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power-down feature controlled by the Chip Enables (either CE0 or CE1) permits the on-chip circuitry of each port to enter a very low standby power mode.
- Dual-port allows simultaneous access of the same memory location
- RapidWrite mode simplifies high-speed consecutive write cycles
- Dual Chip Enables allow for depth expansion without external logic
- Easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device
- Busy and Interrupt flags
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- Separate byte controls for multiplexed bus and bus-matching compatibility
- Sleep mode inputs on both ports
- Includes JTAG functionality
- Single 2.5V (±100mV) power supply for core
- LVTTL-compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
- Available in 256-ball BGA, 208-pin PQFP, and 208-ball fpBGA packages
- Industrial temperature range (–40°C to +85°C) is available
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12.28 M
Listed Part Number
3,000+
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In-stock SKU
15,000+
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