Renesas 70T631S12BFI
Manufacturer No:
70T631S12BFI
Manufacturer:
Renesas
Package:
Description:
256K x 18, 3.3V/2.5V Dual-Port RAM, Interleaved I/O's
Quantity:
In Stock :9556
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
70T631S12BFI Information
Renesas 70T631S12BFI technical specifications, attributes, parameters and parts with similar specifications to Renesas 70T631S12BFI.
- Type
- Parameter
- Lead Count (#)
- 208
- Pb (Lead) Free
- No
- Carrier Type
- Tray
- Access Time (ns)
- 12
- Architecture
- Dual-Port
- Bus Width (bits)
- 18
- Core Voltage (V)
- 2.5
- Density (Kb)
- 4608
- Function
- Busy, Interrupt, JTAG, Master, Semaphore, Slave, Sleep Mode
- I/O Type
- 2.5 V LVTTL, 3.3 V LVTTL
- Type
- Parameter
- Interface
- Async
- Length (mm)
- 15
- MOQ
- 21
- Moisture Sensitivity Level (MSL)
- 4
- Organization
- 256K x 18
- Package Area (mm²)
- 225.0
- Pb Free Category
- e0
- Pitch (mm)
- 0.8
- Pkg. Dimensions (mm)
- 15.0 x 15.0 x 1.4
- Pkg. Type
- CABGA
Download datasheets and manufacturer documentation for Renesas 70T631S12BFI.
The 70T631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.
- Dual-Port allows simultaneous access of the same memory location
- RapidWrite Mode simplifies high-speed consecutive write cycles
- Dual chip enables allow for depth expansion without external logic
- Easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device
- Busy and Interrupt Flags
- On-chip port arbitration logic
- Full hardware support of semaphore signaling between ports on-chip
- Fully asynchronous operation from either port
- Separate byte controls for multiplexed bus and bus matching compatibility
- Sleep Mode Inputs on both ports
- Includes JTAG functionality
- Single 2.5V (±100mV) power supply for core
- LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
- Available in a 256-ball BGA and 208-ball fpBGA
- Industrial temperature range (–40C to +85C) is available
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