Renesas 5V9352PFGI
Manufacturer No:
5V9352PFGI
Manufacturer:
Renesas
Package:
Description:
LVCMOS Clock Generator
Quantity:
In Stock :1783
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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5V9352PFGI Information
Renesas 5V9352PFGI technical specifications, attributes, parameters and parts with similar specifications to Renesas 5V9352PFGI.
- Type
- Parameter
- Pkg. Type
- TQFP
- Lead Count (#)
- 32
- Pb (Lead) Free
- Yes
- Carrier Type
- Tray
- C-C Jitter Max P-P (ps)
- 100
- Core Voltage (V)
- 3.3, 2.5
- Divider Value
- 2, 4, 6
- Feedback Input
- Yes
- Input Freq (MHz)
- 16.67 - 100
- Input Type
- LVCMOS, LVTTL
- Type
- Parameter
- Inputs (#)
- 1
- Length (mm)
- 7.0
- MOQ
- 125
- Moisture Sensitivity Level (MSL)
- 3
- Output Banks (#)
- 3
- Output Freq Range (MHz)
- 16.67 - 200
- Output Signaling
- LVCMOS, LVTTL
- Output Skew (ps)
- 100
- Output Type
- LVCMOS, LVTTL
- Output Voltage (V)
- 3.3, 2.5
Download datasheets and manufacturer documentation for Renesas 5V9352PFGI.
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver targeted for high performance clock tree applications. It uses a PLL to precisely align, in both frequency and phase. The 5V9352 operates at 2.5V and 3.3V. FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: The 5V9352 features three banks of individually configurable outputs. The banks are configured with five, four, and two outputs. The internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1. The output frequency relationship is controlled by the fSEL frequency control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL compatible inputs Unlike many products containing PLLs, the 5V9352 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the 5V9352 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at REFCLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by setting the PLL_EN to high. The 5V9352 is available in Industrial temperature range (-40°C to +85°C).
- Phase-lock loop clock distribution for high performance clock
- tree applications
- Output enable bank control
- External feedback (FBIN) pin is used to synchronize the
- outputs to the clock input signal
- No external RC network required for PLL loop stability
- Operates at 3.3V/2.5V VCC
- Spread Spectrum Compatible
- Operating frequency up to 200MHz
- Compatible with Motorola MPC9352
- Available in 32-pin TQFP package
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
