Renesas 5V2528APGGI
Manufacturer No:
5V2528APGGI
Manufacturer:
Renesas
Package:
Description:
LVCMOS Zero Delay Buffer
Quantity:
In Stock :8222
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Shipped from：HK Warehouse
Expected Shipping：Thu, May 28 - Fri, May 29, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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5V2528APGGI Information
Renesas 5V2528APGGI technical specifications, attributes, parameters and parts with similar specifications to Renesas 5V2528APGGI.
- Type
- Parameter
- Pkg. Type
- TSSOP
- Lead Count (#)
- 28
- Pb (Lead) Free
- Yes
- Carrier Type
- Tube
- C-C Jitter Max P-P (ps)
- 75
- Core Voltage (V)
- 3.3
- Input Freq (MHz)
- 25 - 167
- Input Type
- LVCMOS, LVTTL
- Inputs (#)
- 1
- Length (mm)
- 9.7
- Type
- Parameter
- MOQ
- 100
- Moisture Sensitivity Level (MSL)
- 1
- Output Banks (#)
- 1
- Output Freq Range (MHz)
- 25 - 167
- Output Signaling
- LVCMOS, LVTTL
- Output Skew (ps)
- 150
- Output Type
- LVCMOS, LVTTL
- Output Voltage (V)
- 3.3, 2.5
- Outputs (#)
- 10
- Package Area (mm²)
- 42.7
Download datasheets and manufacturer documentation for Renesas 5V2528APGGI.
The 5V2528 is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The 5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power supply pins. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL outputs. The number of 2.5V outputs is controlled by 3-level input signals G_Ctrl and T_Ctrl, and by connecting the appropriate VDDQ pins to 2.5V or 3.3V. The 3-level input signals may be hard-wired to high-mid-low levels. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input. When the G_Ctrl input is mid or high, the outputs switch in phase and frequency with CLK; when the G_Ctrl is low, all outputs (except FBOUT) are disabled to the logic-low state. Unlike many products containing PLLs, the 5V2528 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the 5V2528 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVDD to ground.
- Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
- 1:10 fanout
- 3-level inputs for output control
- External feedback (FBIN) pin is used to synchronize the
- outputs to the clock input signal
- No external RC network required for PLL loop stability
- Configurable 2.5V or 3.3V LVTTL outputs
- tPD Phase Error at 100MHz to 166MHz: ±150ps
- Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
- Spread spectrum compatible
- Operating Frequency:
- Std: 25MHz to 140MHz
- A: 25MHz to 167MHz
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12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
