Renesas UPD48576209F1-E24-DW1-A
Manufacturer No:
UPD48576209F1-E24-DW1-A
Manufacturer:
Renesas
Package:
Description:
576M-BIT Low Latency DRAM Common I/O
Quantity:
In Stock :8135
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Shipped from：HK Warehouse
Expected Shipping：Wed, Jun 10 - Thu, Jun 11, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
UPD48576209F1-E24-DW1-A Information
Renesas UPD48576209F1-E24-DW1-A technical specifications, attributes, parameters and parts with similar specifications to Renesas UPD48576209F1-E24-DW1-A.
- Type
- Parameter
- Pkg. Type
- TFBGA
- Carrier Type
- Tray
- Architecture
- Low Latency DRAM-II
- Burst Length (Words)
- 2
- Data Width (bits)
- 9
- Density (Kb)
- 576000
- Frequency (Max) (MHz)
- 400
- I/O Voltage (V)
- 1.5/1.8 - 1.5/1.8
- Lead Compliant
- Yes
- Lead Count (#)
- 144
- Type
- Parameter
- Length (mm)
- 18
- MIN Frequency (MHz)
- 175
- MOQ
- 1
- Pb (Lead) Free
- Yes
- Pkg. Dimensions (mm)
- 18 x 11 x 1.2
- Supply Voltage (V)
- 1.8 - 1.8
- Tape & Reel
- No
- Thickness (mm)
- 1.2
- Width (mm)
- 11
- tRC (ns)
- 15
Download datasheets and manufacturer documentation for Renesas UPD48576209F1-E24-DW1-A.
The µPD48576209F1 is a 67, 108, 864-word by 9 bit, the µPD48576218F1 is a 33, 554, 432 word by 18 bit and the µPD48576236F1 is a 16, 777, 216 word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell. The µPD48576209F1, µPD48576218F1 and µPD48576236F1 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and CK#. These products are suitable for application which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration.
- SRAM-type interface
- Double-data-rate architecture
- PLL circuitry
- Cycle time: 1.875 ns @ tRC = 15 ns 2.5 ns @ tRC = 15 ns 2.5 ns @ tRC = 20 ns 3.3 ns @ tRC = 20 ns
- Non-multiplexed addresses
- Multiplexing option is available.
- Data mask for WRITE commands
- Differential input clocks (CK and CK#)
- Differential input data clocks (DK and DK#)
- Data valid signal (QVLD)
- Programmable burst length: 2 / 4 / 8 (x9 / x18 / x36)
- User programmable impedance output (25 Ω - 60 Ω)
- JTAG boundary scan
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)