DSPIC33CK256MP502-I/2N-Microchip-Price, Stock & Datasheet

Microchip’s dsPIC33CK family of digital signal controllers (DSCs) features a 100 MHz dsPIC® DSC core with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of digital power, motor control, advanced sensing and control, high-performance general-purpose and robust applications.

The DSCs simplify the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors.

In the digital power segment, this family of devices is ideal for designing switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency.

This dsPIC33CK family supporting offering core-independent touch capabilities, is well suited for complex touch designs that require up to 256KB flash, functional safety, security, CAN/CAN FD and high level of various function and rich peripheral integration.

The DSCs feature advanced analog for advanced sensor interfacing designs. Offering real-time deterministic performance, the DSCs enable high-performance control applications. The rich feature set in this family of devices also make this family a very good fit for high-performance general-purpose and robust applications.

The dsPIC33CK product family has many hardware features that help simplify functional safety certifications for ASIL-B and SIL-2 focused automotive and industrial safety-critical applications. The family offers ISO 26262 and IEC 61508 Functional Safety packages containing FMEDA report, safety manual, diagnostic libraries and more.

• Learn more about Functional Safety capabilities including hardware, software, and supporting collateral

3.0V to 3.6V
-40ºC to +125ºC, DC to 100 MHz
-40ºC to +150ºC, DC to 70 MHz

Up to 256 KBytes of Program Flash with ECC and Live Update (dual-partition Flash)
Up to 24 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
Modified Harvard architecture with 16-bit data and 24-bit instructions
Code efficient (C and Assembly) CPU architecture designed for real-time applications
16x 16-bit working registers
4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
Single-cycle, mixed-sign 32-bit MUL
Fast 6-cycle hardware 32/16 and 16/16 DIV
Dual 40-bit fixed point Accumulators (ACC) for DSP operations
Single-cycle MAC/MPY with dual data fetch and result write-back
Zero overhead looping support

8 independent PWM pairs (16 total outputs) with up to 250ps resolution
Dead-time insertion for rising and falling edges and dead-time compensation support
Clock chopping for high-frequency operation
Fault and current limit inputs
Flexible trigger configuration for ADC triggering

3 12-bit 3.5 MSPS ADC Modules each with 2 dedicated SARs and 1 shared SAR cores (3 S&Hs)
12, 16, 19, 20 or 24 ADC input channels (depending on package)
4 digital comparators for reducing CPU overhead
4 oversampling filers up to 256x for increased resolution (up to 16-bits)
3 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
Up to 3 op amps with internal connection to ADC Module

Core Independent Touch

Uses Peripheral Trigger Generator (PTG) and High-speed ADCs
Ready-to-use touch library support in MPLAB Code Configurator (MCC)

ISO 26262 and IEC 61508 Functional Safety Ready
ASIL B automotive safety applications – ISO 26262
SIL 2 industrial safety applications – IEC 61508
ISO 26262 and IEC 61508 Functional Safety Packages

CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot
Flash OTP by ICSP Write Inhibit to configure entire Flash as OTP
Option to disable entry to the debug mode
User OTP
Enables implementing robust security use cases together with CryptoAuthentication and CryptoAutomotive devices such as:
Secure Boot
Secure Firmware Upgrade
Secure Communication
Node Authentication and more

10 16-bit timer/counters (up to 4 32-bit)
14 PWM or Output Compare (OC) outputs
9 Input Captures (IC) pins or internal connections from the CLC or Comparator Modules
Peripheral Trigger Generator (PTG) for scheduling complex sequences
2 Quadrature Encoder Interface (QEI) Modules for optical encoder support

3 UARTs (15 Mbps) with automated protocol handling for LIN/J2602, DMX and IrDA®
3 4-wire SPI/I2S up to 40 MHz with dedicated pins
3 I2C Modules (up to 1 Mbps) with SMBus support
CAN Flexible Data Rate (CAN-FD) Module ("50x devices only)
2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
4 DMA channels supporting UART, SPI, ADC, CAN-FD, IC, OC and Timer data transfers

4 Configurable Logic Cell (CLC) Modules with user defined logic gate circuits
Programmable Pin Select (PPS) for peripheral pin function mapping
Parallel Master Port (PMP) for external data expansion
On-chip temperature sensor with direct ADC Module connection

On-chip 8 MHz Fast RC (FRC) and 32 kHz Low-Power RC (LPRC) oscillators
Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)
Fail-Safe Clock Monitor (FSCM) with 8 MHz Back-up Fast RC (BFRC) oscillator
Low-Power management modes - Sleep, Idle and Doze
Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)

In-Circuit and in application programming and debug support (ICSP)
On-chip debug trace buffer and run-time watch with 3 complex and 5 simple breakpoints
IEEE 1149.2 (JTAG) boundary scan support